Prosecution Insights
Last updated: October 22, 2026
Application No. 18/610,150

SEMICONDUCTOR DEVICE WITH SLANTED FIELD PLATE

Non-Final OA §102§103
Filed
Mar 19, 2024
Priority
Oct 10, 2023 — provisional 63/589,040
Examiner
ENAD, CHRISTINE A
Art Unit
Tech Center
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1155 granted / 1367 resolved
+24.5% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 12m
Avg Prosecution
39 currently pending
Career history
1410
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
64.3%
+24.3% vs TC avg
§102
19.5%
-20.5% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1367 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I (Claims 1-10) in the reply filed on September 16, 2026, is acknowledged. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 16, 2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-8, 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patel (US Publication No. 2022/0319840). Regarding claim 1, Patel discloses a semiconductor device Fig 1 and Fig 11H comprising: a semiconductor substrate Fig 1, 10/11/12 ¶0020- 0023; a gate Fig 11H, 15 on a surface of the semiconductor substrate; a drain contact Fig 11H, 14 and a source contact on the semiconductor substrate; and a field plate over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact Fig 11H, 16, the field plate Fig 11H, 48/52 including multiple field plate portions, each of the multiple field plate portions having a uniform respective slope with respect to the surface Fig 11F and 11H, and the multiple field plate portions having different slopes ¶0049. Regarding claim 2, Patel discloses wherein the multiple field plate portions includes a first field plate portion having a first slope and a second field plate portion having a second slope, the first field plate portion is between the gate and the second field plate portion, and the first slope is smaller than the second slope Fig 11F and Fig 11H ¶0047-0049. Regarding claim 3, Patel discloses wherein the first field plate portion abuts a gate contact that electrically couples the gate Fig 11H. Regarding claim 4, Patel discloses wherein the field plate is a first field plate and electrically coupled to a first terminal, and the semiconductor device further comprises a second field plate over the surface, the second field plate has a slope with respect to the surface, and the second field plate is electrically coupled to a second terminal Fig 11F and 11H. Regarding claim 5, Patel discloses wherein the second field plate is between the first field plate and the drain contact Fig 11H. Regarding claim 6, Patel discloses wherein the first terminal is electrically coupled to the gate, and the second terminal is electrically coupled to the source contact Fig 11H. Regarding claim 7, Patel discloses wherein the first and second field plates are separated by a gap Fig 11H. Regarding claim 8, Patel discloses a dielectric structure Fig 11H, 17 on the semiconductor substrate; and an etch stop layer ¶0021 (gate insulator) between the dielectric structure Fig 11H, 17 and the semiconductor substrate, wherein the field plate is on the dielectric structure Fig 11F and 11H. Regarding claim 10, Patel discloses wherein further comprising a Gallium nitride (GaN) layer on the semiconductor substrate, wherein the source contact and the drain contact are electrically coupled to a source and a drain, respectively, in the GaN layer, and the field plate is over the GaN layer Fig 11F and 11H ¶0020-0022, 0032. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Patel (US Publication No. 2022/0319840) in view of Hill et al (US Publication No. 2023/0207641). Regarding claim 9, Patel discloses a layer containing Aluminum silicon oxide ¶0021. Patel discloses all the limitations but silent on the specific material used for the etch stop. Whereas Hill discloses an etch stop that includes an aluminum oxide ¶0018. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the material used, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Mar 19, 2024
Application Filed
Oct 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772488
SEMICONDUCTOR DEVICE AND METHODS OF FORMATION
3y 3m to grant Granted Oct 20, 2026
Patent 12772549
SEMICONDUCTOR DEVICE WITH WORK FUNCTION LAYER
3y 0m to grant Granted Oct 20, 2026
Patent 12772485
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
2y 12m to grant Granted Oct 20, 2026
Patent 12765347
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 3m to grant Granted Oct 13, 2026
Patent 12765049
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
3y 4m to grant Granted Oct 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
95%
With Interview (+10.2%)
1y 12m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1367 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month