CTNF 18/610,219 CTNF 90799 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is responsive to an Application filed on 03/19/2024. Currently, claims 1-25 are examined as below. Information Disclosure Statement Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 03/19/2024. The IDS has been considered. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 7, 10 and 21-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 is indefinite , because the abbreviation “HEMT” in line 1 has not been clearly defined in the claim and the base claim. It is unclear what is necessarily required by the abbreviation “HEMT.” Claim 10 is indefinite , because the abbreviation “HEMT” in line 2 has not been clearly defined in the claim and the base claim. It is unclear what is necessarily required by the abbreviation “HEMT.” Claim 21 is indefinite , because the abbreviation “HEMT” in line 1 has not been clearly defined in the claim and the base claim. It is unclear what is necessarily required by the abbreviation “HEMT.” Independent claim 23 is indefinite , because (1) The abbreviation “IC” in line 1 has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “IC.” (2) The abbreviation “HEMT” in line 3 has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “HEMT.” Independent claim 25 is indefinite , because (1) The abbreviation “IC” in line 1 has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “IC.” (2) The abbreviation “HEMT” in line 3 has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “HEMT.” Note the dependent claims 22 and 24 necessarily inherit the indefiniteness of the claims on which they depend. I. Prior-art rejections based on Chern Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3 and 14-15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by US 2020/0135910 A1 to Chern . PNG media_image1.png 479 679 media_image1.png Greyscale PNG media_image2.png 440 608 media_image2.png Greyscale Regarding independent claim 1 , Chern in Figs. 2, 3P and Annotated Fig. 3P teaches an integrated circuit (IC) 200 (Figs. 2, 3P, ¶ 51, ¶ 58, ¶ 2, semiconductor device 200 of an integrated circuit (IC)) comprising: a semiconductor substrate 210, 310 (Figs. 2, 3P, ¶ 51, ¶ 59, silicon layer 210 corresponding to substrate 310 formed of semiconductor material); a channel layer 230, 330 (Figs. 2, 3P, ¶ 51, ¶ 61, first layer 230 comprising a first III-V semiconductor material corresponding to first III-V semiconductor material layer 330 serves as a channel layer) on the semiconductor substrate 210, 310, the channel layer 230, 330 including a gallium nitride (GaN) material (¶ 52 & ¶ 61, gallium nitride (GaN)); a barrier layer 240, 340 (Figs. 2, 3P, ¶ 52, ¶ 62, second layer 240 comprising a second III-V semiconductor material corresponding to second III-V semiconductor material layer 340 including AlGaN, in which the layer 240, 340 has the same location (i.e., on the channel layer 230, 330) and the same material (i.e., AlGaN) for the barrier layer as the Applicant purported in claim 1 and paragraph 43 in the specification of the present application. Therefore, the layer 240, 340 would function as a barrier layer) on the channel layer 230, 330 (Figs. 2 & 3P); a first semiconductor device 201, T1 (Fig. 2, Annotated Fig. 3P, ¶ 53, ¶ 58, first transistor 201 corresponding to transistor T1) on the semiconductor substrate 210, 310, the first semiconductor device 201, T1 including a first terminal 241, 341 (Fig. 2, Annotated Fig. 3P, ¶ 54, ¶ 63, first polarization modulation portion 241 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 341), over the barrier layer 240, 340, and the first semiconductor device 201, T1 having a first threshold voltage (¶ 54, ¶ 56); and a second semiconductor device 202, T2 (Fig. 2, Annotated Fig. 3P, ¶ 53, ¶ 58, second transistor 202 corresponding to transistor T2) on the semiconductor substrate 210, 310, the second semiconductor device 202, T2 including a second terminal 242, 342 (Fig. 2, Annotated Fig. 3P, ¶ 54, ¶ 65, second polarization modulation layer 242 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 342) over the barrier layer 240, 340, and the second semiconductor device 202, T2 having a second threshold voltage (¶ 54, ¶ 56) different from the first threshold voltage (¶ 54, claim 12), in which the first and second threshold voltages are both positive voltages (¶ 34, ¶ 36-¶ 37, ¶ 39, ¶ 41, ¶ 44-¶ 45, ¶ 49 disclose the threshold voltages are positive voltages). Regarding claim 2 , Chern in Figs. 2 and 3P further teaches the first terminal 241, 341 includes a first semiconductor layer 241, 341 (Figs. 2, 3P, ¶ 54, ¶ 63, first polarization modulation portion 241 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 341), and the second terminal 242, 342 includes a second semiconductor layer 242, 342 (Figs. 2, 3P, ¶ 54, ¶ 65, second polarization modulation layer 242 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 342). Regarding claim 3 , Chern in Figs. 2 and 3P further teaches each of the first and second semiconductor layers 241, 341, 242, 342 includes a p-type doped GaN layer 241, 341, 242, 342 (¶ 54, ¶ 63, ¶ 65; see the rejection of claim 1 as noted above). Regarding claim 14 , Chern in Fig. 2 and Annotated Fig. 3P further teaches the first semiconductor device 201, T1 includes a first metal contact 251, 351 (Fig. 2, Annotated Fig. 3P, ¶ 54, first gate structure 251 corresponding to first gate 351 formed of metal material) on the first terminal 241, 341, the first metal contact 251, 351 has a same lateral footprint as the first terminal 241, 341 (Fig. 2 & Annotated Fig. 3P, the width of the layer 251, 351 is about the same as the width of the layer 241, 341 i.e., same lateral footprint); and wherein the second semiconductor device 202, T2 includes a second metal contact 252, 352 (Fig. 2, Annotated Fig. 3P, ¶ 53, ¶ 69, second gate structure 252 corresponding to second gate 352 formed of metal materials) on the second terminal 242, 342, the second metal contact 252, 352 has a different lateral footprint from the second terminal 242, 342 (Fig. 2 & Annotated Fig. 3P, the layer 242, 342 is not aligned with the layer 252, 352 i.e., different lateral footprint). Regarding claim 15 , Chern in Fig. 2 further teaches the first and second terminals 241, 242 have different compositions (¶ 54, ¶ 56, portions 241 and 242 include different p-type doping materials) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Chern. Regarding claim 8 , Chern in Figs. 2, 3P and Annotated Fig. 3P further teaches wherein the first terminal 241, 341 includes a first semiconductor layer 241, 341 (Fig. 2, Annotated Fig. 3P, ¶ 54, ¶ 63, first polarization modulation portion 241 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 341) over a surface of the barrier layer 240, 340, the first semiconductor layer 241, 341 having a first thickness over the surface of the barrier layer 240, 340 (Figs. 2 & 3P); and wherein the second terminal 242, 342 includes a second semiconductor layer 242, 342 (Fig. 2, Annotated Fig. 3P, ¶ 54, ¶ 65, second polarization modulation layer 242 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 342) over the surface of the barrier layer 240, 340, the second semiconductor layer 242, 342 having a second thickness over the surface of the barrier layer 240, 340 (Figs. 2 & 3P). Chern does not explicitly disclose the second thickness being different from the first thickness. However, it would have been obvious to form the first and second thicknesses within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. ( In Gardner v. TEC Systems, Inc. , 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claim 16 , Chern in Figs. 2 and 3P further teaches the first terminal 241, 341 includes a first semiconductor layer 241, 341 (Figs. 2, 3P, ¶ 54, ¶ 63, first polarization modulation portion 241 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 341), the second terminal 242, 342 includes a second semiconductor layer 242, 342 (Figs. 2, 3P, ¶ 54, ¶ 65, second polarization modulation layer 242 having a p-type doped GaN (pGaN) corresponding to pGaN gate stack 342). Chern does not explicitly disclose the first and second semiconductor layers have different dopant concentrations. However, Chern teaches a general condition in which the first semiconductor layer 241, 341 has a p-type doped GaN (¶ 54, ¶ 63) and the second semiconductor layer 242, 342 has a p-type doped GaN (¶ 54, ¶ 65), in which each of the first semiconductor layer 241, 341 and the second semiconductor layer 242, 342 would have a dopant concentration. According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller , 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Here, since Chern teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of the first and second semiconductor layers having different dopant concentrations produce unexpected results that are different in kind and not different in degree, said general conditions taught by Chern renders claim 16 obvious. 07-21-aia AIA Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chern in view of US 2008/0237638 A1 to Bito . Regarding claim 18 , Chern in Figs. 2, 3P and Annotated Fig. 3P teaches the semiconductor substrate 210, 310 and the first and second semiconductor devices 201, T1, 202, T2. However, Chern does not explicitly disclose the semiconductor substrate including an isolation structure between the first and second semiconductor devices. Bito recognizes a need for electrically separating a first transistor and a second transistor (¶ 31 & ¶ 43). Bito satisfies the need by providing a semiconductor substrate 1, 2 (Fig. 1, ¶ 34-¶ 35, a collective of GaAs substrate 1 and buffer layer 2, which is an AlGaAs layer) including an isolation structure 22 (Fig. 1, ¶ 43, isolation region 22) between first and second semiconductor devices FET 1, FET 2 (Fig. 1, ¶ 31, first field effect transistor FET 1 and second field effect transistor FET 2 of a semiconductor device 50). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the semiconductor substrate taught by Chern with the isolation structure taught by Bito, so as to electrically separate a first transistor and a second transistor (Bito: ¶ 31 & ¶ 43) . 07-21-aia AIA Claim s 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chern in view of US 2015/0034962 A1 to Cao et al. (“Cao”) . Regarding independent claim 23 , Chern in Figs. 1-2 teaches an IC 100 (Fig. 1 & ¶ 18, circuit 100) including: a first HEMT 174 (Fig. 1, ¶ 28, low voltage enhancement-mode high electron mobility transistor (LV E-HEMT) 174), the first HEMT 174 coupled between a power terminal 103 (Fig. 1, ¶ 30, power supply pin VDD 103) and a switching terminal 175 (Fig. 1, ¶ 18, power switch HEMT 175); a second HEMT 172 (Fig. 1, ¶ 28, low voltage enhancement-mode high electron mobility transistor (LV E-HEMT) 172), the second HEMT 172 coupled between the switching terminal 175 and a ground terminal 111 (Fig. 1, ¶ 20, ground Vss 111); and a diode 143 (Fig. 1, ¶ 28, ¶ 31, transistor 143 is a diode-connected HEMT), the diode 143 coupled between the switching terminal 175 and the ground terminal 111, the diode 143 having a different threshold voltage from at least one of the first HEMT 174 and the second HEMT 172 (¶ 45, threshold voltage of transistor 143 is different from threshold voltage of the second HEMT 172). However, Chern does not explicitly disclose the IC including a semiconductor substrate and components of the IC are disposed on the semiconductor substrate. Cao recognizes a need for providing a structure on which an integrated circuit can be formed and supported (Fig. 1, ¶ 20). Cao satisfies the need by providing an integrated circuit 100 including a semiconductor substrate 302 (Fig. 1, ¶ 20), and devices (i.e., 101, 201) of the integrated circuit 100 are formed on the substrate 302 (Fig. 1, ¶ 20). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the semiconductor substrate taught by Cao with the circuit taught by Chern, so as to provide a structure on which an integrated circuit can be formed and supported (Cao: Fig. 1, ¶ 20). Regarding claim 24 , Chern in Fig. 1 further teaches the diode 143 is a diode-connected HEMT 143 (Fig. 1, ¶ 28, ¶ 31, transistor 143 is a diode-connected HEMT). II. Prior-art rejections based on Xia Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 4, 9 and 13 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by US 2016/0300835 A1 to Xia et al. (“Xia”) . PNG media_image3.png 780 679 media_image3.png Greyscale Regarding independent claim 1 , Xia in Fig. 10 teaches an integrated circuit (IC) 1000 (Fig. 10, ¶ 93, ¶ 96, abstract, structure 1000 is an integrated circuit) comprising: a semiconductor substrate 602 (¶ 76, substrate layer 602); a channel layer 606 (¶ 76, channel layer 606) on the semiconductor substrate 602 (Fig. 10), the channel layer 606 including a gallium nitride (GaN) material (¶ 47, channel layer includes GaN); a barrier layer 608 (¶ 78, cap layer 608 covers the channel layer 606 would block passage of external elements to the channel layer 606 i.e., barrier layer) on the channel layer 606 (Fig. 10); a first semiconductor device 1010 (¶ 93, transistor 1010) on the semiconductor substrate 602 (Fig. 10), the first semiconductor device 1010 including a first terminal 1012 (Fig. 10, ¶ 93, recessed gate 1012) over the barrier layer 608 (Fig. 10, the first terminal 1012 covers (i.e., over) a side surface of the barrier layer 608), and the first semiconductor device 1010 having a first threshold voltage (¶ 95-¶ 96, transistor 1010 has a threshold voltage); and a second semiconductor device 1020 (¶ 93, transistor 1020) on the semiconductor substrate 602 (Fig. 10), the second semiconductor device 1022 including a second terminal 1022 (¶ 93, recessed gate 1022) over the barrier layer 608 (Fig. 10, the second terminal 1022 covers (i.e., over) a side surface of the barrier layer 608), and the second semiconductor device 1020 having a second threshold voltage (¶ 95-¶ 96, transistor 1020 has a threshold voltage) different from the first threshold voltage (¶ 95-¶ 96), in which the first and second threshold voltages are both positive voltages (¶ 62, ¶ 84, ¶ 93, E-mode transistor 1010, 1020 have positive threshold voltages). Regarding claim 2 , Xia in Fig. 10 further teaches the first terminal 1012 includes a first semiconductor layer 1012 (Fig. 10, ¶ 58, gate is formed of semiconductor), and the second terminal 1022 includes a second semiconductor layer 1022 (Fig. 10, ¶ 58, gate is formed of semiconductor). Regarding claim 4 , Xia in Fig. 10 further teaches the first semiconductor device 1010 is a first enhancement mode high electron mobility transistor (HEMT) 1010 (Fig. 10, ¶ 37, ¶ 93, transistor 1010 is an E-mode transistor having a gate recess 1012 which includes high-electron-mobility transistor (HEMT)), the first terminal 1012 is a first gate 1012 (¶ 93, recessed gate 1012) of the first enhancement mode HEMT 1010, and the first enhancement mode HEMT 1010 includes a first drain 1018 (Fig. 10, ¶ 93, ohmic contact 1018 for D i.e., drain) and a first source 1016 (Fig. 10, ¶ 93, ohmic contact 1016 for S i.e., source); and wherein the second semiconductor device 1020 is a second enhancement mode HEMT 1020 (Fig. 10, ¶ 37, ¶ 93, transistor 1020 is an E-mode transistor having a gate recess 1022 which includes high-electron-mobility transistor (HEMT)), the second terminal 1022 is a second gate 1022 (¶ 93, recessed gate 1022) of the second enhancement mode HEMT 1020, and the second enhancement mode HEMT 1020 includes a second drain 1028 (Fig. 10, ¶ 93, ohmic contact 1028 for D i.e., drain) and a second source 1026 (Fig. 10, ¶ 93, ohmic contact 1026 for S i.e., source). Regarding claim 9 , Xia in Fig. 10 further teaches the first terminal 1012 is on the barrier layer 608 (Fig. 10), and the second terminal 1022 extends into the barrier layer 608 (Fig. 10). Regarding claim 13 , Xia in Fig. 10 further teaches the first terminal 1012 is a first gate 1012 (¶ 93, gate 1012) having a first gate length (Fig. 10, vertical length), and the second terminal 1022 is a second gate 1022 (¶ 93, gate 1022) having a second gate length (Fig. 10, vertical length) different from the first gate length (Fig. 10) . Allowable Subject Matter 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claims 5-7, 11-12, 17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim. Claim 5 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 5, wherein the first enhancement mode HEMT includes a first metal contact on the first semiconductor layer, the first metal contact forming a junction with the first semiconductor layer, the junction being a Schottky junction or an ohmic junction; and wherein the first enhancement mode HEMT includes a first diode terminal electrically coupled to the first source and to the first metal contact, and a second diode terminal electrically coupled to the first drain . Claim 6 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 6, the first terminal being configured as a first diode terminal, and the first semiconductor device includes a third terminal configured as a second diode terminal . Claim 7 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, wherein the first semiconductor device is a first depletion mode HEMT, the first terminal being a first gate of the first depletion mode HEMT, the first terminal being on a first dielectric layer; and wherein the second semiconductor device is a second depletion mode HEMT, the second terminal being a second gate of the second depletion mode HEMT, the second gate being on a second dielectric layer . Claim 11 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 11, wherein: the barrier layer includes: a first barrier sub-layer over the channel layer, the first barrier sub-layer having an opening therethrough; and a second barrier sub-layer over the first barrier sub-layer and conformally in the opening to form a recess; the first terminal extends into the recess and on the second barrier sub-layer . Claim 12 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, wherein: the channel layer has a first recess; the barrier layer is conformally in the first recess forming a second recess; the first terminal extends into the second recess; and the second terminal is on the barrier layer and is laterally outside of the second recess . Claim 17 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 17, wherein the first terminal is on a first dielectric layer, the second terminal is on a second dielectric layer, and the first and second dielectric layers have different dielectric constants . Claim 19 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 19, the IC further comprises a third semiconductor device on the semiconductor substrate, the third semiconductor device having a negative third threshold voltage . Claim 20 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 20, the IC further comprises a third semiconductor device on the semiconductor substrate, the third semiconductor device having a positive third threshold voltage . 07-43-02 AIA Claim s 10 and 21-22 are rejected , but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claim 10 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 10, a third metal contact on the semiconductor layer, the third metal contact electrically coupled to the drain . Claim 21 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 21, wherein the first semiconductor device is a first depletion mode HEMT, and the second semiconductor device is a second depletion mode HEMT . Claim 22 would be allowable , because claim 22 depends from the allowable claim 21. 07-43-01 AIA Claim 25 are rejected , but would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action. PNG media_image4.png 517 823 media_image4.png Greyscale PNG media_image5.png 473 883 media_image5.png Greyscale Regarding independent claim 25 , US 2014/0015591 A1 to Chen et al. (“Chen”) in Figs. 2 and 5 teaches an IC 200, 500 (Figs. 2, 5, ¶ 48 & ¶ 61, circuit 200 or system 500) including: a semiconductor substrate 302 (Fig. 5, ¶ 61, substrate layer 302); a first depletion mode HEMT 300, 104 (Fig. 5, ¶ 54, ¶ 48, depletion-mode high electron mobility transistor (D-HEMT) semiconductor device 300 corresponds to semiconductor device 104) on the semiconductor substrate 302, the first depletion mode HEMT 300 coupled between a power terminal 108 (Fig. 2, ¶ 51, input bias voltage 108) and a clamp terminal (Fig. 2, ¶ 82, voltage at the gate of E-mode power HEMT 102 is clamped and the D-mode HEMT 104 clamps. That is, the terminal between 104s and 102g is a clamp terminal), the first depletion mode HEMT 300, 104 having a first threshold voltage (¶ 87, threshold voltage for the D-HEMT); an enhancement mode HEMT 400, 102 (Figs. 2, 5, ¶ 49, ¶ 58, enhancement-mode high electro mobility transistor (E-HEMT) semiconductor device 400 corresponds to semiconductor device 102) on the semiconductor substrate 302, the enhancement mode HEMT 400, 102 coupled to the clamp terminal (Fig. 2, the terminal between 104s and 102g), the enhancement mode HEMT 400, 102 having a gate terminal 102g (Figs. 2, 5, ¶ 49, ¶ 58, gate electrode 318’, 102g). However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 25, the enhancement mode HEMT coupled between the clamp terminal and a ground terminal; and a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input electrically coupled to the clamp terminal, the second comparator input electrically coupled to a reference terminal, and the comparator output electrically coupled to the gate terminal, the comparator including a second depletion mode HEMT on the semiconductor substrate, the second depletion mode HEMT 400, 102 having a second threshold voltage different from the first threshold voltage . Therefore, independent claim 25 would be allowable . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2022/0029008 A1 to Yang et al. US 10,516,043 B1 to Sriram et al . Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.L./Examiner, Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817 Application/Control Number: 18/610,219 Page 2 Art Unit: 2817
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