Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 and 20 in the reply filed on 6/30/2025 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-8 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai (20210305226).
Regarding claim 1, Tsai teaches a semiconductor device assembly, comprising:
a first semiconductor die (fig. 2D: 150A) having a first contact, a second contact, and a third contact (please see multiple contacts 145’) coupled with circuitry at the first semiconductor die (par. 49; further please see fig. 2D);
a first stack of semiconductor dies (fig. 2D: either 150b1-150d1 or 150b2-150d2) coupled, through the first contact (each stacks is connected to 145’), with the first semiconductor die at a first lateral location, the first stack of semiconductor dies including a second semiconductor die (please see middle chip fig. 2D) distal from the first semiconductor die and having a fourth contact (please see 145’ on 150b1-150d1 or 150b2-150d2) coupled with circuitry at the second semiconductor die, the fourth contact exposed at a first distal end of the first stack of semiconductor dies opposite the first semiconductor die (please see fig. 2D which shows this limitation);
a second stack of semiconductor dies (fig. 2D: either 150b1-150-d1 or 150b2-150d2) coupled, through the second contact (each stack is connected to 145’), with the first semiconductor die at a second lateral location, the second stack of semiconductor dies including a third semiconductor die (please see middle chip in fig. 2D) distal from the first semiconductor die and having a fifth contact (please see 145’ on 150b1-150d1 or 150b2-150d2) coupled with circuitry at the third semiconductor die, the fifth contact exposed at a second distal end of the second stack of semiconductor dies opposite the first semiconductor die (please see fig. 2D which shows this limitation);
a dielectric material (fig. 2D: 151a-151d between chip stacks 150b1-150d1 and 150b2-150d2) disposed at a portion of the first semiconductor die that is exposed beyond a first footprint of the first stack of semiconductor dies and beyond a second footprint of the second stack of semiconductor dies (please see specified 151a-151d mirrors this limitation); and
a through dielectric via (fig. 2D: 153b-153d between chip stacks 150b1-150d1 and 150b2-150d2 are TIVs) extending entirely through the dielectric material to the third contact and configured to provide power to the circuitry at the first semiconductor die (please see specified 153b-153d mirrors this limitation).
Regarding claim 3, Tsai teaches a semiconductor device assembly of claim 1, wherein: the third contact comprises a buried contact (please see 145’ in fig. 2D); and the through dielectric via extends at least partially through the first semiconductor die to the buried contact (please see 153b which extends into PM2a).
Regarding claim 4, Tsai teaches a semiconductor device assembly of claim 1, further comprising: a sixth contact coupled with the circuitry at the first semiconductor die (please see multiple 145’); and an additional through dielectric via (there are multiple 153b-153d) extending entirely through the dielectric material to the sixth contact, the additional through dielectric via configured to communicate signaling to or from the circuitry at the first semiconductor die (please see fig. 2D).
Regarding claim 6, Tsai teaches a semiconductor device assembly of claim 1, further comprising a redistribution layer (RDL2d) disposed over (if 150’ is flipped RDL2d will be over chip stacks a first die) the first stack of semiconductor dies, the second stack of semiconductor dies, and the dielectric material, the redistribution layer coupled with the fourth contact, the fifth contact, and the through dielectric via (please see fig. 2D).
Regarding claim 7, Tsai teaches a semiconductor device assembly of claim 1, wherein: the dielectric material is disposed over the first distal end of the first stack of semiconductor dies and the second distal end of the second stack of semiconductor dies; and the fourth contact and the fifth contact are exposed through the dielectric material (please see fig. 2D).
Regarding claim 8, Tsai teaches a semiconductor device assembly of claim 1, wherein: the first semiconductor die comprises a logic die (par. 55); and the first stack of semiconductor dies and the second stack of semiconductor dies comprise memory dies (par. 55).
Regarding claim 20, Tsai teaches a semiconductor device assembly, comprising:
a redistribution layer (fig. 2D: RDL2d);
a first stack of semiconductor dies (fig. 2D: either 150b1-150d1 or 150b2-150d2) coupled with the redistribution layer at a first lateral location;
a second stack of semiconductor dies (fig. 2D: either 150b1-150d1 or 150b2-150d2) coupled with the redistribution layer at a second lateral location;
a first semiconductor die (fig. 2D: 150A) having a larger footprint than the first stack of semiconductor dies and the second stack of semiconductor dies combined, the first semiconductor die coupled with the first stack of semiconductor dies and the second stack of semiconductor dies at a distal end opposite the redistribution layer (please see fig. 2D);
a dielectric material (fig. 2D: 151a-151d between chip stacks 150b1-150d1 and 150b2-150d2) disposed between the redistribution layer, the first stack of semiconductor dies, the second stack of semiconductor dies, and the first semiconductor die (please see fig. 2D); and
a through dielectric via (fig. 2D: 153b-153d between chip stacks 150b1-150d1 and 150b2-150d2 are TIVs) extending through the dielectric material between the redistribution layer and the first semiconductor die, the through dielectric via configured to provide power from the redistribution layer to the first semiconductor die (please see fig. 2D).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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