DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant elected, without traverse, Species 1 (shown in Figs. 1, 2, and 4) in the response (filed 08/12/26) to Restriction Requirements. Applicant stated that Claims 1-5, 7-15, and 18-20 are read on the elected species. However, Claim 15, citing that the plurality of second posts are on a top surface of the dam structure, is directed to Species 6 (shown in Figs. 9-10); Claim 17, citing that the at least one semiconductor chip includes a stack of two chips, is directed to Species 4 (Fig. 6).
Status of Claims
Claims 6 and 15-17 are withdrawn from further consideration as being drawn to nonelected inventions.
Claims 1-5, 7-14, and 18-20 are examined on merits herein.
Specification
The disclosure is objected to because of the following informalities:
Paragraphs 0038 and 0061 of the published application state that a chip may include silicon or a semiconductor; however, silicon is also a semiconductor.
Appropriate correction of paragraphs is required.
Claim Objections
Claims 1, 13, and 19 are objected to because of the following informalities:
Independent Claims 1, 13, and 19 recite: “a dam structure on a top surface of the first package substrate, the dam structure extending and surrounding a region of the first package substrate”. Examiner suggests changing the recitation to: “a dam structure on a top surface of the first package substrate, the dam structure extending and surrounding a region of the top surface of the first package substrate”, since a dam structure that is disposed on a top surface of the package substrate cannot surround a region of this substrate extending in a depth from the top surface.
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Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-5, 7-14, and 18-20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (regards as the invention.
In re Claims 1, 13, 14 and 19: Claim 1 recites: “the plurality of posts are in the region of the top surface of the first package substrate”. Claims 13, 14, and 19 have similar recitations. The recitations are unclear, since a post is a three-dimensional structure, while a surface is a two-dimensional structure, and a three-dimensional structure cannot fit into the two-dimensional structure.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation of Claim 1 was interpreted as: “the plurality of posts are disposed on the region of the top surface of the first package substrate”, and the similar recitations of Claims 13, 14, and 19 were interpreted in a similar manner.
In re Claims 8 and 19: Claim 8 recites: “a recessed groove in a bottom surface” and Claim 19 has a similar recitation. The recitation is unclear, since a groove is a three-dimensional element, while a surface is a two-dimensional element, and a three-dimensional element cannot be created in a two-dimensional element.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: “a recessed groove passing through a bottom surface”
In re Claims 2-5, 7, 9-12, 18, and 20: Claims 2-5, 7, 9-12, 18, and 20 are rejected under 35 U.S.C. 112(b) at least due to dependency on one of independent Claims 1, 13, or 19.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
As far as the claims are understood, Claims 1, 4, 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2021/0242190).
In re Claim 1, Oh teaches a semiconductor package (Abstract), comprising (Fig. 8D):
a first package substrate 111 (paragraph 0022);
a dam structure 112dm (paragraph 0091) on a top surface of the first package substrate 122, the dam structure 112dm extending and surrounding a region of the first package substrate 122 (paragraphs 0091-0093);
a semiconductor chip 140 (paragraph 0026) on the top surface of the first package substrate 122;
a plurality of posts 154 (paragraph 0063) on the top surface of the first package substrate 111, and surrounding the semiconductor chip (surrounding, at least, in the cross-sectional view), the plurality of posts 154 being in the region of the top surface of the first package substrate 111 surrounded by the dam structure 112dm (paragraphs 0091-0093); and
an underfill layer 160 (paragraph 0063) between the semiconductor chip 140 and the first package substrate 111, the underfill layer 160 surrounding a lower portion of each of the plurality of posts 154.
In re Claim 4, Oh teaches the semiconductor package as claimed in Claim 1, wherein (Fig. 8D):
the first package substrate 111 includes a plurality of upper bump pads 122 (paragraph 0024) on the top surface thereof,
some of the plurality of posts 154 are in contact with respective ones of the plurality of upper bump pads 122, and
the underfill layer 160 surrounds contact portions between the plurality of posts 154 and the respective ones of the plurality of upper bump pads 122.
In re Claim 5, Oh teaches the semiconductor package as claimed in Claim 1, wherein (Fig. 8D) the underfill layer 160 is in the region of the top surface of the first package substrate 111 surrounded by the dam structure 112dm, the underfill layer 160 being in contact with an inner wall of the dam structure 112dm.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Wang et al. (US 2015/0262900).
In re Claim 2, Oh teaches the semiconductor package of Claim 1 as cited above, including the dam formed over and along an edge of the first package substrate, but does not teach that the dam structure has a quadrangular ring shape extending along sides of the top surface of the first package substrate, and that a horizontal width of the dam structure in a direction that is perpendicular to an extension direction of the dam structure is about 20 µm to about 50 µm.
Wang teaches (Figs. 3-4) that a dam structure 60 (paragraph 0016) has a quadrangular ring shape extending along sides of a top surface of a first package substrate, and that a horizontal width of the dam structure in a direction that is perpendicular to an extension direction of the dam structure is about 20 µm to about 50 µm – Wang teaches a range from 5 µm to about 40 µm, which overlaps the claimed range, and in accordance with MPEP 2144.05 Obviousness of Similar and Overlapping Ranges, Amounts, and Proportions. I. OVERLAPPING, APPROACHING, AND SIMILAR RANGES, AMOUNTS, AND PROPORTIONS: In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Oh and Wang teach analogous arts directed to a dam structure created over and along sides/edges of a substrate, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying/understanding the Oh device in view of the Wang device, since they are from the same field of endeavor, and Wang created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the semiconductor package of Oh by creating the dam structure in the quadrangular ring shape (and, obviously, creating the first package substrate in this shape) if such shape is desired for the manufacturer. Note that In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to create the dam structure with a horizontal width taught by Wang, to enable such parameter as a dam structure width.
In re Claim 3, Oh teaches the semiconductor package of Claim 1 as cited above, including the dam structure, but does not teach that a height of the dam structure in a vertical direction is about 10 µm to about 18 µm.
Wang teaches (Figs. 3-4, paragraph 0052) that a height of a dam structure 60 in a vertical direction can be chosen from a range from 8 µm to about 20 µm, which overlaps the claimed range. In accordance with MPEP 2144.05 Obviousness of Similar and Overlapping Ranges, Amounts, and Proportions. I. OVERLAPPING, APPROACHING, AND SIMILAR RANGES, AMOUNTS, AND PROPORTIONS: In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to create the dam structure with a vertical height taught by Wang, to enable such parameter as a dam structure vertical height.
As far as the claims are understood, Claims 7 and 11-12 are rejected under 35 .S.C. 103 as being unpatentable over Oh in view of Jin et al. (US 2021/0398908).
In re Claim 7, Oh teaches the semiconductor package of Claim 1 as cited above and further comprising (Fig. 8D) a second package substrate 300 (paragraph) above the semiconductor chip 140 and the plurality of posts 154.
Oh does not teach that the second package substrate 300 includes an interposer - his interposer 200 (paragraph 0064) is between the first and second packages and is connected to first and second package substrates.
Jin teaches a semiconductor package comprising (Fig. 15) a second substrate 311 being an interposer (paragraph 0138).
Oh and Jin teach analogous arts directed to a package-on-package structure comprised of an interposer, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Oh package in view of the Jin package, since they are from the same field of endeavor, and Jin created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Oh package by creating its second package substrate being an interposer substrate, when it is desirable to reduce such parameter of the semiconductor package as a package thickness.
In re Claim 11, Oh/Jin teaches the semiconductor package of Claim 7 as cited above, with Jin teaching the second substrate being an interposer.
Jin further teaches (Fig. 15, paragraph 0030) that a portion of a plurality of posts 150 electrically connect a first package substrate – comprised a connection structure 110 (paragraph 0054) to a second package substrate 311.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to use at least a portion of the plurality of posts of the first package substrate for electrical connection between the first and second package substrate, when electrical connection between the first and second package substrate is desirable.
In re Claim 12, Oh/Jin teaches the semiconductor package of Claim 11 as cited above, including the portion of the plurality of posts that electrically connect the first package substrate to the second package substrate.
Oh does not explicitly teach that some posts include at least one of a copper post and a solder ball. But both – Oh and Jin teach that vias of a device include copper (paragraph 0028 of Oh and Jin (Fig. 15, paragraphs 0065, 0066.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the Oh posts from copper to enable creation of these posts, when it is desirable to limit a number of conductive materials used for the semiconductor package
As far as the claims are understood, Claims 8-9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Oh/Jin in view of Mok et al. (US 2007/0187810).
In re Claim 8, Oh/Jin teaches the semiconductor package of Claim 7 as cited above but does not teach that the second package substrate further includes a recessed groove in a bottom surface thereof.
Mok teaches (Fig. 4f; see also Figs. 4a-through 4e for some numbers, paragraph 0052) that a second package substrate – comprising a core layer 450 - includes a recessed groove 475 passing through a bottom surface of the second package substrate.
Oh/Jin and Mok teach analogous arts directed to a package-on-package structure, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Oh/Jin package in view of the Mok package, since they are from the same field of endeavor, and Mok created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Oh/Jin device by creating through a bottom of the second package substrate – a groove, either in order to reduce an overall thickness of the package (Mok, paragraphs 0008-0009) or if such shape of the second package substrate is desired by the manufacturer. Note that in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 9, Oh/Jin/Mok teaches the semiconductor package of Claim 8 as cited above with the recess/groove created in the second package substrate per Mok, who teaches (Fig. 4, paragraph 0046) that distance between opposite side walls of the recessed groove is greater than a horizontal length of a semiconductor chip 435 (paragraph 0052), the semiconductor chip being vertically below the recessed groove 475.
As far as the claims are understood, Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Oh.
In re Claim 13, Oh teaches a semiconductor package, comprising (Fig. 8D):
a first package substrate 111 (paragraph 0022);
a dam structure 112dm (paragraphs 0091-0093) on a top surface of the first package substrate 111, the dam structure extending (as being formed along an entire edge of substrate 111) and surrounding a region of the first package substrate;
at least one semiconductor chip 140 (paragraph 0026) on the top surface of the first package substrate 111;
a plurality of first posts 154 (paragraph 0063) – as closest to chip 140 - and a plurality of second posts 154 – as furthest from 140 - on the top surface of the first package substrate 111 and surrounding the at least one semiconductor chip 140;
an underfill layer 160 (paragraph 0058) between the at least one semiconductor chip 140 and the first package substrate 111 and surrounding a lower portion of each of the plurality of first posts 154; and
a second package substrate – comprised a base board layer 310 (paragraph 0070) - on the plurality of first posts 154 and the plurality of second posts 154, wherein:
the plurality of first posts 154 are in the region of the top surface of the first package substrate surrounded by the dam structure 112dm,
the plurality of first posts 154 electrically connect the first package substrate 111 to the second package substrate (comprising 310) through interposer 220 (paragraph 00065) - since the first package substrate 111 is connected to the interposer 200 including its upper pattern 222 (Fig. 3K, paragraph 0064), while 222 is connected to contacts 352 of the second substrate (Fig. 3L-3M, paragraphs 0066 -0072) , and
the plurality of second posts 154 physically support the second package substrate – as it is obvious, all posts 154 support the second package substrate.
In re Claim 14, Oh teaches the semiconductor package of Claim 13 as cited above, wherein (Fig. 8D):
the plurality of second posts – 154 that are furthest from chip 140 - are in the region of the top surface of the first package substrate 11 surrounded by the dam structure 112dm, and
the underfill layer 160 surrounds a lower portion of each of the plurality of second posts.
As far as the claims are understood, Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Oh in view of Choi et al. (US 2012/0211885).
In re Claim 18, Oh teaches the semiconductor package of Claim 13 as cited above but does not teach a molding layer filling between the first package substrate and the second package substrate and surrounding the at least one semiconductor chip.
Choi teaches (Fig. 7) a molding layer 170 (paragraphs 0055 and 0057) filling between a first package substrate 120 and a second package substrate 210 and surrounding semiconductor chip 130.
Oh and Choi teach analogous arts directed to a package-on-package structure, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Oh package in view of the Choi package, since they are from the same field of endeavor, and Choi created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Oh package of Claim 13 by adding a molding layer filling between the first package substrate and the second package substrate and surrounding the semiconductor chip, wherein it is desirable sealing a lateral exterior of the first semiconductor package (Choi, paragraph 0057).
In re Claim 19, Oh teaches a semiconductor package, comprising (Fig. 8D):
a first package substrate 111 (paragraph 0022);
a dam structure 112dm (paragraph 0093) on a top surface of the first package substrate 111, the dam structure extending and surrounding a region of the first package substrate (paragraphs 0091-0093);
at least one lower semiconductor chip 140 (paragraph 0026) on the top surface of the first package substrate 111;
a plurality of first posts 154 (that are closer to chip 140, paragraph 0063) and a plurality of second posts 154 (that are further from chip 140) on the top surface of the first package substrate 111 and surrounding (at least, as it is shown, - in a cross-section) the at least one lower semiconductor chip 140;
an underfill layer 160 (paragraph 0059) between the at least one lower semiconductor chip 140 and the first package substrate 111, surrounding a lower portion of each of the plurality of first posts 154, and being in contact with an inner wall of the dam structure 112dm;
a second package substrate – comprising a base layer 310 (paragraph 0070) on the plurality of first posts 154 and the plurality of second posts 154; and
an upper semiconductor chip 344 (paragraph 0071) on the second package substrate, wherein:
the plurality of first posts 154 are in the region of the top surface of the first package substrate 111 surrounded by the dam structure 112dm,
the plurality of first posts 154 electrically connect the first package substrate 111 to the second package substrate – through interposer 200 (paragraphs 0065-0073), and
the plurality of second posts 154 physically support the second package substrate – as well as the plurality of first posts.
Oh does not teach that the second package substrate includes a recessed groove in a bottom surface (e.g., “passing through the bottom surface”) and that the at least one lower semiconductor chip is vertically below the recessed groove of the second package substrate.
Mok teaches (Fig. 4f; see also Figs. 4a-through 4e for some numbers, paragraph 0052) that a second package substrate – comprising a core layer 450 - includes a recessed groove 475 passing through a bottom surface of the second package substrate and that a lower semiconductor chip 435 is vertically below the recessed groove of the second package substrate.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Oh device by creating through a bottom of the second package substrate – a groove and to dispose the lower semiconductor chip vertically below the recessed groove, either in order to reduce an overall thickness of the package (Mok, paragraphs 0008-0009) or if such shape of the second package substrate is desired by the manufacturer. Note that in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
Allowable Subject Matter
Claims 10 and 20, as interpreted, contain allowable subject matter.
Reason for Indicating Allowable Subject Matter
Re Claim 10: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 10 as: “a distance between a top surface of the semiconductor chip and a bottom of the recessed groove in a vertical direction is about 40 µm to about 70 µm”, in combination with other limitations of Claim 10 and in combination with limitations of Claims 1, 7, and 9, on which Claim 10 depends.
Re Claim 20: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 20 as: “a distance between a top surface of the semiconductor chip and a bottom of the recessed groove in a vertical direction is about 40 µm to about 70 µm”, in combination with other limitations of Claim 20 and in combination with limitations of Claim 19, on which Claim 20 depends.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 08/24/26
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