DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of applicant’s Amendment, filed 22 January 2026. The changes and remarks disclosed therein have been considered.
No claims have been cancelled and claims 11-14 are newly added by Amendment. Therefore, claims 1-14 are pending in the application.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “a common string select line”, as recited in claims 1, 6, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-14 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1, 6 are recites the limitations “a common string select line”. This limitation cannot be found in the disclosure as originally filed and is therefore new matter. Claims 2-5, 7-14 depend from claims 1, 6 and therefore contain the same new matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hara et al (US 9,299,438 B2 hereinafter “Hara”) in view of Hosono (US 2016/0240264 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Hara, for example in Figs. 1- 38, discloses a method of operating (see for example in Figs. 6-9, 11-12 related in Figs. 1-5, 10, 13-38) a memory device (e.g., memory device 200; in Figs. 1-2 related in Figs. 3-38), comprising: selecting a target memory cell (e.g., memory cell on WL0/WL1/WL2/WL3/WL4/WL5/WL6/WL7; in Figs. 8-9 related in Figs. 1-7, 10-38) and at least one replicated memory cell (within string 16-1; in Fig. 8 related in Figs. 1-7, 9-38) belonging to a target memory string (e.g., string 16-1; in Fig. 8 related in Figs. 1-7, 9-38), the target memory string comprising a plurality of serially connected memory cells (e.g., MT0-MT3/MT4-MT7; in Figs. 3, 8 related in Figs. 1-2, 4-7, 9-38) coupled to a common bit line (e.g., common BL0 is connected to string 16 in SU0 and string in SU1; in Figs. 3, 8 related in Figs. 1-2, 4-7, 9-38), and a common ground select line (e.g.,SGD0-SGS3 are common connected to 0V or ground voltage; in Fig. 8 related in Figs. 1-7, 9-38); replicating a target weight value written into the target memory cell to the at least one replicated memory cell (e.g., “1” data/”0” data; in Fig. 8 related in Figs. 1-7, 9-38), wherein the target memory cell and the at least one replicated memory cell store the target weight value (e.g., “1” data/”0” data; in Fig. 8 related in Figs. 1-7, 9-38); and in response to a command of reading or computing on the target memory cell received by the memory device (via command user interface 14; in Figs. 1-2 related in Figs. 3-38), performing reading or computing on the target memory cell and the at least one replicated memory cell simultaneously (e.g., at t2; in Fig. 9 related in Figs. 1-8, 10-38).
However, Hara is silent with regard to a common string select line.
In same field of endeavor, Hosono, for example in Figs. 1-18, discloses a common string select line (e.g., SG1_0 and SG1_1 are common connected to 2C; in Fig. 4 related in Figs. 1-3, 5-18).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hara such as semiconductor memory device (see for example in Figs. 1-38 of Hara) by incorporating the teaching of Hosono such as semiconductor memory device (see for example in Figs. 1-18 of Hosono), for the purpose of controlling the applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line (Hosono, see Abstract).
The structure in of the prior art (Hara and Hosono) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
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Regarding claim 2, the above Hara/Hosono, combination discloses wherein the target memory cell and the at least one replicated memory cell are serially connected within the target memory string (see for example in Fig. 8 related in Figs. 1-7, 9-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 3, the above Hara/Hosono, combination discloses wherein the target memory cell is coupled to a target word line (see for example in Fig. 8 related in Figs. 1-7, 9-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above); the at least one replicated memory cell is coupled to at least one replicated word line (see for example in Fig. 8 related in Figs. 1-7, 9-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above), and in reading the target memory cell, both the target word line and the at least one replicated word line are simultaneously selected to simultaneously activate the target memory cell and the at least one replicated memory cell (see for example in Figs. 21-22 related in Figs. 1-20, 23-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 4, the above Hara/Hosono, combination discloses wherein in performing computing on the target memory cell, the target word line and the at least one replicated word line receive the same input value (see for example in Figs. 8-9 related in Figs. 1-7, 10-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 5, the above Hara/Hosono, combination discloses wherein the memory device is a 2D/3D NAND flash memory; and the memory device is a non-volatile memory (see for example in Figs. 3-4 related in Figs. 1-2, 5-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding Independent Claim 6, Hara, for example in Figs. 1-38, discloses a memory device (e.g., memory device 200; in Figs. 1-2 related in Figs. 3-38) comprising: a memory array (e.g., memory array 2; in Figs. 2-3, 8 related in Figs. 1, 4-7, 9-38); and a memory controller coupled to the memory array (e.g., sequencer 13 within block 200; in Figs. 1-2 related in Figs. 3-38), wherein the memory controller is configured to: selecting a target memory cell (e.g., memory cell on WL0/WL1/WL2/WL3/WL4/WL5/WL6/WL7; in Figs. 8-9 related in Figs. 1-7, 10-38) and at least one replicated memory cell (within string 16-1; in Fig. 8 related in Figs. 1-7, 9-38) belonging to a target memory string (e.g., string 16-1; in Fig. 8 related in Figs. 1-7, 9-38), the target memory string comprising a plurality of serially connected memory cells coupled to a common bit line (e.g., common BL0 is connected to string 16 in SU0 and string in SU1; in Figs. 3, 8 related in Figs. 1-2, 4-7, 9-38), and a common ground select line (e.g.,SGD0-SGS3 are common connected to 0V or ground voltage; in Fig. 8 related in Figs. 1-7, 9-38); replicating a target weight value written into the target memory cell to the at least one replicated memory cell (e.g., “1” data/”0” data; in Fig. 8 related in Figs. 1-7, 9-38), wherein the target memory cell and the at least one replicated memory cell store the target weight value (e.g., “1” data/”0” data; in Fig. 8 related in Figs. 1-7, 9-38); and in response to a command of reading or computing on the target memory cell received by the memory device (via command user interface 14; in Figs. 1-2 related in Figs. 3-38), performing reading or computing on the target memory cell and the at least one replicated memory cell simultaneously (e.g., at t2; in Fig. 9 related in Figs. 1-8, 10-38).
However, Hara is silent with regard to a common string select line.
In same field of endeavor, Hosono, for example in Figs. 1-18, discloses a common string select line (e.g., SG1_0 and SG1_1 are common connected to 2C; in Fig. 4 related in Figs. 1-3, 5-18).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hara such as semiconductor memory device (see for example in Figs. 1-38 of Hara) by incorporating the teaching of Hosono such as semiconductor memory device (see for example in Figs. 1-18 of Hosono), for the purpose of controlling the applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line (Hosono, see Abstract).
Regarding claim 7, the above Hara/Hosono, combination discloses wherein the target memory cell and the at least one replicated memory cell are serially connected within the target memory string (see for example in Fig. 8 related in Figs. 1-7, 9-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 8, the above Hara/Hosono, combination discloses wherein the target memory cell is coupled to a target word line (see for example in Fig. 8 related in Figs. 1-7, 9-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above); the at least one replicated memory cell is coupled to at least one replicated word line (see for example in Fig. 8 related in Figs. 1-7, 9-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above), and in reading the target memory cell, both the target word line and the at least one replicated word line are simultaneously selected to simultaneously activate the target memory cell and the at least one replicated memory cell (see for example in Figs. 21-22 related in Figs. 1-20, 23-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 9, the above Hara/Hosono, combination discloses wherein in performing computing on the target memory cell, the target word line and the at least one replicated word line receive the same input value (see for example in Figs. 8-9 related in Figs. 1-7, 10-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 10, the above Hara/Hosono, combination discloses wherein the memory device is a 2D/3D NAND flash memory; and the memory device is a non-volatile memory (see for example in Figs. 8-9 related in Figs. 1-7, 10-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 11, the above Hara/Hosono, combination discloses wherein replicating the target weight value into the target memory cell is performed during a programming operation of the target memory cell (see for example in Figs. 8-9 related in Figs. 1-7, 10-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 12, the above Hara/Hosono, combination discloses wherein in response to the command of reading or computing on the target memory cell received by the memory device (see for example in Figs. 8-9 related in Figs. 1-7, 10-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above), simultaneously activating a target word line and a replicated word line corresponding to the target memory cell and the replicated memory cell to perform reading or computing on the target memory cell and the at least one replicated memory cell simultaneously (see for example in Figs. 8-9 related in Figs. 1-7, 10-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 13, the above Hara/Hosono, combination discloses wherein the memory controller is configured to: replicate the target weight value into the target memory cell during a programming operation of the target memory cell (see for example in Figs. 8-9 related in Figs. 1-7, 10-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Regarding claim 14, the above Hara/Hosono, combination discloses wherein the memory controller is configured to: in response to the command of reading or computing on the target memory cell received by the memory device (see for example in Figs. 1-2 related in Figs. 3-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above), simultaneously activate a target word line and a replicated word line corresponding to the target memory cell and the replicated memory cell to perform reading or computing on the target memory cell and the at least one replicated memory cell simultaneously (see for example in Figs. 21-22 related in Figs. 1-20, 23-38 of Hara and also see in Fig. 4 related in Figs. 1-3, 5-18 of Hosono, as discussed above).
Applicants are reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Response to Arguments
Applicant's arguments filed 22 January 2026 have been fully considered but
are moot because the new ground of rejection is made in view of Hosono (US 2016/0240264 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THA-O H BUI/Primary Examiner, Art Unit 2825 02/03/2026