DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species II in the reply filed on 15 July 2026 is acknowledged. The traversal is on the ground(s) that there is no search burden for the Examiner and that the species are not mutually exclusive. This is found partially persuasive because, although there is a search burden on the Examiner, the restriction was done incorrectly and is therefore improper.
The requirement has been WITHDRAWN IN FULL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 20 March 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, “the edge” in line 4 lacks proper antecedent basis and is therefore unclear.
Regarding claim 21, “photocharges” in line 10 is unclear as “charges” has been mentioned previously in the same claim. Is this limitation referring to the same charges mentioned previously or different photocharges? In light of the specification, the Examiner is interpreting this limitation to be referring to the same charges mentioned previously.
Regarding claim 22, “photocharges” in line 14 is unclear as “charges” has been mentioned previously in the same claim. Is this limitation referring to the same charges mentioned previously or different photocharges? In light of the specification, the Examiner is interpreting this limitation to be referring to the same charges mentioned previously.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 9, and 14-16 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Lee et al. (USPGPub 20160056200 A1).
Regarding claim 1, Lee teaches an image sensor comprising: a semiconductor substrate (414) including a pixel array including a plurality of pixels (1/2/3/4/5/6/7) (see figures 4 and 10, photodiodes 122 and 124 located in a semiconductor substrate (not labeled) and photodiodes 423 and 424 located in semiconductor substrate 414; ¶65, The unit pixel 1 may be formed by stacking a micro lens 115, a color filter 113, an anti-reflection layer 111, and a semiconductor substrate; and ¶56, unit pixels 1 according to embodiments of the present inventive concepts may constitute the pixel array 810 of FIG. 1 in a matrix pattern); a first photoelectric conversion device (121/221/321/521) and a second photoelectric conversion device (122/222/322/522) inside the semiconductor substrate (414) and included in each of the plurality of pixels (1/2/3/4/5/6/7) (see figures 3, 5-7, 9, 11, and 13, unit pixels 1-7 comprising a plurality of photodiodes 121-124, 221-222, 321-324, and 521-522 disposed in the semiconductor substrate); microlenses (115/415) on the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) (see figures 4 and 10, microlenses 115 and 415); and a device isolation structure (135/235/335/535/130/231/330/531) between the plurality of pixels (1/2/3/4/5/6/7) and between the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) (see figures 3, 5-7, 9, 11, and 13, first DTIs 135, 235, 335, and 535 surrounding each pixel unit and partial DTIs 130, 231, 330, and 531 being disposed between adjacent photodiodes), the device isolation structure (135/235/335/535/130/231/330/531) opening a part between the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522), including an open region at each edge of the plurality of pixels (1/2/3/4/5/6/7), and being continuous in the pixel array (see figures 6-7 and 9, openings (unlabeled) left by partial DTIs on the edge of each pixel unit).
Regarding claim 2, Lee teaches the image sensor of claim 1, wherein a ground contact (246/342/343/442/443/346/446/542/642) configured to provide a ground voltage to the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) is in the open region (see figures 6, 9, 11, and 13, ground 246, 342-343, 442-443, 346, 446, 542, and 642 disposed in the openings; and ¶109, The grounds 342 and 343 may supply ground voltage required for an operation of the unit pixels 5. For example, the grounds 342 and 343 may supply the ground voltage to one side end of the photo diode 320).
Regarding claim 3, Lee teaches the image sensor of claim 1, wherein a floating diffusion region (260) configured to accumulate photocharges generated by each of the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) is in the open region (see figures 6-7, floating diffusion node 260 disposed in the opening; ¶64, The floating diffusion node 160 may be a node in which photo charges generated by the photo diode 120 are transmitted and accumulated through the transfer transistor TG; and ¶86, floating diffusion node 260 may be electrically connected with the first photo diode 221 and the second photo diode 222. That is, the first and second photo diodes 221 and 222 may share a floating diffusion node 260).
Regarding claim 4, Lee teaches the image sensor of claim 1, wherein an active region or gate of a transistor (361/365/463/462) included in each of the plurality of pixels (1/2/3/4/5/6/7) is in the open region (see figures 9 and 11, transistors 361, 365, 463, and 462 disposed in the opening).
Regarding claim 5, Lee teaches the image sensor of claim 4, wherein the transistor (361/365/463/462) comprises at least one of a reset transistor configured to reset a floating diffusion region configured to accumulate photocharges generated in the first photoelectric conversion device and the second photoelectric conversion device, an amplification transistor configured to amplify a signal according to the photocharges accumulated in the floating diffusion region, and a selection transistor configured to be connected to the amplification transistor and output a pixel signal (see figures 9 and 11, transistors 361, 365, 463, and 462 disposed in the opening; ¶108, The first supplement transistors 361 and 365 may be, for example, any one of a dummy transistor, a reset transistor, a drive transistor, and a select transistor; and claim 10, a reset transistor configured to reset the floating diffusion node according to a reset control signal).
Regarding claim 9, Lee teaches an image sensor comprising: a first photoelectric conversion device (121/221/321/521) and a second photoelectric conversion device (122/222/322/522) inside a semiconductor substrate (414) and included in each of a plurality of pixels (1/2/3/4/5/6/7) (see figures 4 and 10, photodiodes 122 and 124 located in a semiconductor substrate (not labeled) and photodiodes 423 and 424 located in semiconductor substrate 414; see figures 3, 5-7, 9, 11, and 13, unit pixels 1-7 comprising a plurality of photodiodes 121-124, 221-222, 321-324, and 521-522 disposed in the semiconductor substrate; ¶65, The unit pixel 1 may be formed by stacking a micro lens 115, a color filter 113, an anti-reflection layer 111, and a semiconductor substrate; and ¶56, unit pixels 1 according to embodiments of the present inventive concepts may constitute the pixel array 810 of FIG. 1 in a matrix pattern); microlenses (115/415) on the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) (see figures 4 and 10, microlenses 115 and 415); a first device isolation structure (135/235/335/535) between the plurality of pixels (1/2/3/4/5/6/7) (see figures 3, 5-7, 9, 11, and 13, first DTIs 135, 235, 335, and 535 surrounding each pixel unit); and a second device isolation structure (130/231/330/531) between the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) (see figures 3, 5-7, 9, 11, and 13, partial DTIs 130, 231, 330, and 531 being disposed between adjacent photodiodes), the second device isolation structure (130/231/330/531) opening a part between the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522), including an internal open region at each edge of the plurality of pixels (1/2/3/4/5/6/7), and the first device isolation structure (135/235/335/535) and the second device isolation structure (130/231/330/531) contacting each other (see figure 7, opening (unlabeled) left by partial DTIs on the edge of each pixel unit and wherein the first DTI 235 is in contact with partial DTI 232; and NOTE: the other embodiments comprise first and partial DTIs contacting one another through the substrate).
Regarding claim 14, Lee teaches the image sensor of claim 9, wherein a ground contact (246/342/343/442/443/346/446/542/642) configured to provide a ground voltage to the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) is in the internal open region (see figures 6, 9, 11, and 13, ground 246, 342-343, 442-443, 346, 446, 542, and 642 disposed in the openings; and ¶109, The grounds 342 and 343 may supply ground voltage required for an operation of the unit pixels 5. For example, the grounds 342 and 343 may supply the ground voltage to one side end of the photo diode 320).
Regarding claim 15¸ Lee teaches the image sensor of claim 9, wherein a floating diffusion region (260) configured to accumulate photocharges generated by each of the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) is in the internal open region (see figures 6-7, floating diffusion node 260 disposed in the opening; ¶64, The floating diffusion node 160 may be a node in which photo charges generated by the photo diode 120 are transmitted and accumulated through the transfer transistor TG; and ¶86, floating diffusion node 260 may be electrically connected with the first photo diode 221 and the second photo diode 222. That is, the first and second photo diodes 221 and 222 may share a floating diffusion node 260).
Regarding claim 16, Lee teaches the image sensor of claim 9, wherein an active region or gate of a transistor (361/365/463/462) included in each of the plurality of pixels (1/2/3/4/5/6/7) is in the internal open region (see figures 9 and 11, transistors 361, 365, 463, and 462 disposed in the opening).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPGPub 20160056200 A1) in view of Lim et al. (USPGPub 20210242270 A1).
Regarding claim 6, Lee teaches the image sensor of claim 1, further comprising a ground contact (246/342/343/442/443/346/446/542/642) configured to provide a ground voltage applied to the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) (¶109, The grounds 342 and 343 may supply ground voltage required for an operation of the unit pixels 5. For example, the grounds 342 and 343 may supply the ground voltage to one side end of the photo diode 320). However, Lee fails to explicitly teach wherein the ground contact is under the edge of each of the first photoelectric conversion device and the second photoelectric conversion device.
However, Lim teaches wherein the ground contact (GND1-GND4) is under the edge of each of the first photoelectric conversion device (PX1) and the second photoelectric conversion device (PX2) (see figure 7, ground electrodes GND1-GND4 disposed below photoelectric conversion areas PX1-PX4; and claim 16, a first ground voltage electrode vertically aligned with the first photodiode to overlap the first photodiode; a second ground voltage electrode vertically aligned with the second photodiode to overlap the second photodiode).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee to incorporate the teachings of Lim to provide the ground contact below the photoelectric conversion element because the mere rearrangement of parts would not have modified the operation of the device and is an obvious matter of choice (MPEP 2144.04 VI C).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPGPub 20160056200 A1) in view of Jung et al. (USPGPub 20220109015 A1).
Regarding claim 8, Lee teaches an open region at each edge of the plurality of pixels (1/2/3/4/5/6/7) (see figures 6-7 and 9, openings (unlabeled) left by partial DTIs on the edge of each pixel unit). However, Lee fails to explicitly teach a passivation layer in the open region and doped with p-type impurities.
However, Jung teaches a passivation layer in the open region and doped with p-type impurities (¶35, a passivation layer formed in the open region of the second isolation layer and doped with P-type impurities may improve linearity of full wells of the first pixel PX1 and the second pixel PX2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee to incorporate the teachings of Jung to further include a passivation layer in the opening in order to improve linearity of full wells of the first pixel PX1 and the second pixel PX2 (Jung, ¶35).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPGPub 20160056200 A1) in view of Satake et al. (USPGPub 20240379691 A1).
Regarding claim 10, Lee teaches the first device isolation structure (135/235/335/535) between the plurality of pixels (1/2/3/4/5/6/7) (see figures 3, 5-7, 9, 11, and 13, first DTIs 135, 235, 335, and 535 surrounding each pixel unit). However, Lee fails to explicitly teach wherein the first device isolation structure comprises an external open region configured to open a portion between adjacent pixels.
However, Satake teaches wherein the first device isolation structure (310b/340) comprises an external open region configured to open a portion between adjacent pixels (100) (see figures 9-11, element separation walls 310b and element separation walls 340 together isolating adjacent imaging elements 100 (i.e. pixels), the walls comprising openings).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee to incorporate the teachings of Satake to provide openings between adjacent pixels in order to share circuitry between pixels, allowing interpolation of pixel signals, decreasing captured image deterioration (Satake, see ¶¶4-5).
Regarding claim 12, Lee as modified by Satake teaches the image sensor of claim 10, wherein a floating diffusion region (Lee 260 | Satake FD/601) configured to accumulate photocharges generated in each of first photoelectric conversion devices (Lee 121/221/321/521) and second photoelectric conversion devices (Lee 122/222/322/522) included in two adjacent pixels (Lee 1/2/3/4/5/6/7 | Satake 100) is in the external open region (Lee, ¶64, The floating diffusion node 160 may be a node in which photo charges generated by the photo diode 120 are transmitted and accumulated through the transfer transistor TG; and ¶86, floating diffusion node 260 may be electrically connected with the first photo diode 221 and the second photo diode 222. That is, the first and second photo diodes 221 and 222 may share a floating diffusion node 260; and Satake, see figures 13 and 16, floating diffusion region FD and/or 601 disposed in opening and receiving signals from the two adjacent pixels and their respective photoelectric conversion elements).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPGPub 20160056200 A1) in view of Satake et al. (USPGPub 20240379691 A1) as applied to claim 10 above, and further in view of Jin et al. (USPGPub 20220406825 A1).
Regarding claim 11, Lee as modified by Satake teaches wherein the first device isolation structure (Lee 135/235/335/535 | Satake 310b/340) comprises an external open region configured to open a portion between adjacent pixels (Lee 1/2/3/4/5/6/7 | Satake 100) (Satake, see figures 9-11, element separation walls 310b and element separation walls 340 together isolating adjacent imaging elements 100 (i.e. pixels), the walls comprising openings); and a ground contact (Lee 246/342/343/442/443/346/446/542/642) (Lee, ¶109, The grounds 342 and 343 may supply ground voltage required for an operation of the unit pixels 5. For example, the grounds 342 and 343 may supply the ground voltage to one side end of the photo diode 320). However, the combination fails to explicitly teach wherein a ground contact configured to provide a ground voltage to the adjacent pixels is in the external open region.
However, Jin teaches wherein a ground contact (GR) configured to provide a ground voltage to the adjacent pixels is in the external open region (see figure 6, ground GR disposed in an opening of the external isolation structure; and ¶105, the ground impurity regions GR may be disposed between the first parts P1 of the pixel isolation structure PIS and between the second parts P2 of the pixel isolation structure PIS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lee and Satake to incorporate the teachings of Jin to provide the ground node in the external opening in order to share the ground node between pixels, thereby decreasing the amount of space taken up on a chip by individual ground nodes.
Claims 20 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPGPub 20160056200 A1) in view of Jung et al. (USPGPub 20220239854 A1) (hereinafter Jung2).
Regarding claim 20, Lee teaches an image sensor comprising: a first chip including a semiconductor substrate (414) including a device isolation structure (135/235/335/535/130/231/330/531) isolating a plurality of pixels (1/2/3/4/5/6/7) (see figures 3, 5-7, 9, 11, and 13, first DTIs 135, 235, 335, and 535 surrounding each pixel unit and partial DTIs 130, 231, 330, and 531 being disposed between adjacent photodiodes; and ¶116, The image sensor 1060 may be integrated in one chip together with the processor 1010 or may be integrated in a different chip from the processor 1010); the first chip including a first photoelectric conversion device (121/221/321/521) and a second photoelectric conversion device (122/222/322/522) inside the semiconductor substrate (414) and included in each of the plurality of pixels (1/2/3/4/5/6/7) (see figures 4 and 10, photodiodes 122 and 124 located in a semiconductor substrate (not labeled) and photodiodes 423 and 424 located in semiconductor substrate 414; see figures 3, 5-7, 9, 11, and 13, unit pixels 1-7 comprising a plurality of photodiodes 121-124, 221-222, 321-324, and 521-522 disposed in the semiconductor substrate; ¶65, The unit pixel 1 may be formed by stacking a micro lens 115, a color filter 113, an anti-reflection layer 111, and a semiconductor substrate; and ¶56, unit pixels 1 according to embodiments of the present inventive concepts may constitute the pixel array 810 of FIG. 1 in a matrix pattern); and microlenses (115/415) on the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) (see figures 4 and 10, microlenses 115 and 415), the device isolation structure (135/235/335/535/130/231/330/531) being between the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522) (see figures 3, 5-7, 9, 11, and 13, partial DTIs 130, 231, 330, and 531 being disposed between adjacent photodiodes), and the device isolation structure (135/235/335/535/130/231/330/531) opening a part between the first photoelectric conversion device (121/221/321/521) and the second photoelectric conversion device (122/222/322/522), including an internal open region at each edge of the plurality of pixels (1/2/3/4/5/6/7), and continuous in the first chip (see figures 6-7 and 9, openings (unlabeled) left by partial DTIs on the edge of each pixel unit). However, Lee fails to explicitly teach a second chip under the first chip and comprising a negative voltage generator configured to apply a negative voltage to the device isolation structure.
However, Jung2 teaches a second chip (CH1) under the first chip (CH2) and comprising a negative voltage generator (120) configured to apply a negative voltage to the device isolation structure (¶6, The row driver is configured to adjust, for each of preset periods, sizes and application timings of a negative voltage applied to the device isolation structure; and ¶98, The pixel array (110 of FIG. 1) may be formed in the first chip CH1, and in the second chip CH2, a logic circuit, e.g., the row driver 120, the readout circuit 130, the ramp signal generator 140, and the timing controller 150, may be formed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee to incorporate the teachings of Jung2 to apply a negative voltage to the isolation structures because [w]hen a negative voltage is applied to the device isolation structure PIS by the conductive contact 119, holes in the substrate 100p may move towards an interface of the device isolation structure PIS and accumulate at the interface. Accordingly, the occurrence of the dark current may decrease in the image sensor (Jung2, ¶65).
Regarding claim 23, Lee as modified by Jung2 teaches the image sensor of claim 20, wherein a ground contact (Lee 246/342/343/442/443/346/446/542/642) configured to provide a ground voltage to the first photoelectric conversion device (Lee 121/221/321/521) and the second photoelectric conversion device (Lee 122/222/322/522) is in the internal open region (Lee, see figures 6, 9, 11, and 13, ground 246, 342-343, 442-443, 346, 446, 542, and 642 disposed in the openings; and ¶109, The grounds 342 and 343 may supply ground voltage required for an operation of the unit pixels 5. For example, the grounds 342 and 343 may supply the ground voltage to one side end of the photo diode 320).
Regarding claim 24, Lee as modified by Jung2 teaches the image sensor of claim 20, wherein a floating diffusion region (Lee 260) configured to accumulate photocharges generated by each of the first photoelectric conversion device (Lee 121/221/321/521) and the second photoelectric conversion device (Lee 122/222/322/522) is in the internal open region (Lee, see figures 6-7, floating diffusion node 260 disposed in the opening; ¶64, The floating diffusion node 160 may be a node in which photo charges generated by the photo diode 120 are transmitted and accumulated through the transfer transistor TG; and ¶86, floating diffusion node 260 may be electrically connected with the first photo diode 221 and the second photo diode 222. That is, the first and second photo diodes 221 and 222 may share a floating diffusion node 260).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPGPub 20160056200 A1) in view of Jung et al. (USPGPub 20220239854 A1) (hereinafter Jung2) as applied to claim 20 above, and further in view of Jung et al. (USPGPub 20220109015 A1).
Regarding claim 21, Lee as modified by Jung2 teaches the image sensor of claim 20, wherein the first chip further comprises: a floating diffusion region (Lee 160/260/360/460/560/660) (Lee, see figures 5-7, 9, 11, and 13, floating diffusions 160, 260, 360, 460, 560, and 660); a first transmission transistor (Lee 151) and a second transmission transistor (Lee 152) configured to transmit, to the floating diffusion region (Lee 160/260/360/460/560/660), charges generated by the first photoelectric conversion device (Lee 121/221/321/521) and the second photoelectric conversion device (Lee 122/222/322/522) (Lee, ¶50, The transfer transistors 151 to 154 may serve to transfer the photo charge generated by the photo diodes 121 to 124 to a gate terminal of the drive transistor 162 through the floating diffusion node FD; and ¶8, The pixel circuit may include a first transfer transistor coupled to the first photo diode and positioned on the first photo diode, a second transfer transistor coupled to the second photo diode and positioned on the second photo diode, and a floating diffusion node coupled to both the first and second transfer transistors); a reset transistor (Lee 161) configured to reset the floating diffusion region (Lee 160/260/360/460/560/660) (Lee, see figure 2, reset transistor 161; and claim 10, a reset transistor configured to reset the floating diffusion node according to a reset control signal); and a selection transistor (Lee 163) configured to output a pixel signal (Lee, see figure 2, select transistor 163; ¶54, The select transistor 163 may transfer current generated from the drive transistor 162 to a column line C1; and see remainder of ¶54 for further details). However, the combination fails to explicitly teach an amplification transistor configured to amplify a signal according to photocharges accumulated in the floating diffusion region; and the selection transistor connected to the amplification transistor.
However, Jung teaches an amplification transistor (SF) configured to amplify a signal according to photocharges accumulated in the floating diffusion region (FD) (¶49, The amplification transistor SF may be controlled according to the number of photocharges accumulated in the floating diffusion region FD The amplification transistor SF may be controlled according to the number of photocharges accumulated in the floating diffusion region FD. The amplification transistor SF, which is a buffer amplifier, may buffer a signal according to a charge stored in the floating diffusion region FD. In an embodiment, the amplification transistor SF amplifies a potential change in the floating diffusion region FD and outputs an amplified potential change as a pixel signal VOUT); and the selection transistor (SX) connected to the amplification transistor (SF) (¶50, The selection transistor SX includes a drain terminal connected to a source terminal of the amplification transistor SF, and may output the pixel signal VOUT to the CDS 151 through the column output line in response to a selection signal SELS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lee and Jung2 to incorporate the teachings of Jung to further include an amplification transistor in order to boost the pixel signal with low noise.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPGPub 20160056200 A1) in view of Jung et al. (USPGPub 20220239854 A1) (hereinafter Jung2) as applied to claim 20 above, and further in view of Yamashita (USPGPub 20250211879 A1).
Regarding claim 22, Lee as modified by Jung2 teaches the image sensor of claim 20, wherein the first chip further comprises a floating diffusion region (Lee 160/260/360/460/560/660) (Lee, see figures 5-7, 9, 11, and 13, floating diffusions 160, 260, 360, 460, 560, and 660; and ¶116, The image sensor 1060 may be integrated in one chip together with the processor 1010 or may be integrated in a different chip from the processor 1010); and a first transmission transistor (Lee 151) and a second transmission transistor (Lee 152) configured to transmit, to the floating diffusion region (Lee 160/260/360/460/560/660), charges generated by the first photoelectric conversion device (Lee 121/221/321/521) and the second photoelectric conversion device (Lee 122/222/322/522) (Lee, ¶50, The transfer transistors 151 to 154 may serve to transfer the photo charge generated by the photo diodes 121 to 124 to a gate terminal of the drive transistor 162 through the floating diffusion node FD; and ¶8, The pixel circuit may include a first transfer transistor coupled to the first photo diode and positioned on the first photo diode, a second transfer transistor coupled to the second photo diode and positioned on the second photo diode, and a floating diffusion node coupled to both the first and second transfer transistors), the image sensor further comprising a reset transistor (Lee 161) configured to reset the floating diffusion region (Lee 160/260/360/460/560/660) (Lee, see figure 2, reset transistor 161; and claim 10, a reset transistor configured to reset the floating diffusion node according to a reset control signal); and a selection transistor (Lee 163) (see figure 2, select transistor 163). However, the combination fails to explicitly teach further comprising a third chip between the first chip and the second chip, the third chip comprises a reset transistor; an amplification transistor configured to amplify a signal according to photocharges accumulated in the floating diffusion region; and a selection transistor, connected to the amplification transistor, configured to output a pixel signal.
However, Jung teaches further comprising a third chip (20) between the first chip (10) and the second chip (30) (see figure 1, first substrate 10 (i.e. first chip), second substrate 20 (i.e. third chip), and third substrate 30 (i.e. second chip)), the third chip (20) comprises a reset transistor (201) (see figure 2B, third chip 20 comprising reset transistor 201); an amplification transistor (202) configured to amplify a signal according to photocharges accumulated in the floating diffusion region (103) (see figure 2B, third chip 20 comprising amplification transistor 202; and ¶65, The amplification transistor 202 generates a signal (voltage signal) of a voltage corresponding to a level of charge held in the floating diffusion 103 as the pixel signal. When the selection transistor 203 is turned on, the amplification transistor 202 amplifies the potential of the floating diffusion 103 and outputs a voltage); and a selection transistor (203), connected to the amplification transistor (202), configured to output a pixel signal (see figure 2B, third chip 20 comprising selection transistor 203; and ¶65, The selection transistor 203 controls an output timing of the pixel signal from the readout circuit 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lee and Jung2 to incorporate the teachings of Yamashita to have three separate chips, as well as the elements disposed on separate chips as claimed because the mere rearrangement of parts would not have modified the operation of the device and is an obvious matter of choice (MPEP 2144.04 VI C).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 13, the prior art of record individually or combined fails to teach the image sensor of claims 10 and 1 as claimed, more specifically in combination with wherein a floating diffusion region configured to accumulate photocharges generated in each of first photoelectric conversion devices and second photoelectric conversion devices included in four adjacent pixels is in the external open region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang et al. (USPGPub 20240145498 A1): Yang teaches a pixel unit having a shared floating diffusion disposed in an opening in the isolation elements (see figure 2B).
Chuang et al. (USPGPub 20230402477 A1): Chuang teaches a pixel unit having either a shared floating diffusion or ground disposed in an opening in the isolation elements (see figures 6 and 7).
Fujita et al. (USPGPub 20220359585 A1): Fujita teaches a pixel unit having a shared ground disposed in an opening in the isolation elements (see figure 2).
Moon et al. (USPGPub 20220109012 A1): Moon teaches a pixel unit having a shared floating diffusion disposed in an opening in the isolation elements (see figure 7A).
Kitano (USPGPub 20200068155 A1): Kitano teaches a floating diffusion shared between two unit pixels comprising a total of 8 photoelectric conversion elements.
Sasaki et al. (JP 2014033054 A): Sasaki teaches a plurality of different shared floating diffusion layouts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIN R GARBER whose telephone number is (571)272-4663. The examiner can normally be reached M-F 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Y Epps can be reached at (571)272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIN R GARBER/Examiner, Art Unit 2878
Prosecution Insights