DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Higashitani et al. (U.S. Publication No. 2013/0130468 A1; hereinafter Higashitani)
With respect to claim 1, Higashitani discloses a semiconductor device, comprising: a peripheral circuit structure [860/190]; a stack structure [192] vertically overlapping the peripheral circuit structure; and a separation structure penetrating through the stack structure (see Figure 1B; separation between [160/170] and [180]), wherein the stack structure includes a plurality of blocks [161/163],[181/193] spaced apart from each other by a first portion of the separation structure, wherein each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction (see ¶[0086]), and wherein the plurality of blocks include first blocks and a plurality of capacitor blocks [182/184] disposed between first blocks adjacent to each other among the first blocks (see Figure 28A).
With respect to claim 2, Higashitani discloses wherein the plurality of capacitor blocks are spaced apart from each other by a second portion of the separation structure, wherein each of the plurality of capacitor blocks includes a capacitor, and wherein the capacitor includes capacitor electrodes including the conductive layers and capacitor dielectric layers including the insulating layers (See Figure 1B and 29A).
With respect to claim 3, Higashitani discloses wherein the peripheral circuit structure includes a first peripheral circuit, and wherein the first peripheral circuit is included in a circuit by being electrically connected to a first capacitor of a first capacitor block of the plurality of capacitor blocks, and the first peripheral circuit vertically overlaps at least a portion of the first capacitor (See Figure 29A; peripheral circuit below capacitor).
With respect to claim 4, Higashitani discloses wherein a side surface of at least one capacitor block of the plurality of capacitor blocks is surrounded by the separation structure (see Figure 1B; space between 182 and 184).
With respect to claim 5, Higashitani discloses wherein each of the plurality of blocks has a side surface surrounded by the separation structure (See Figure 1B).
With respect to claim 6, Higashitani discloses wherein the first blocks include a plurality of memory blocks and at least one dummy block (see ¶[0086]), and wherein the conductive layers in the plurality of memory blocks include word lines (see ¶[0062]).
With respect to claim 7, Higashitani discloses wherein the plurality of memory blocks include a first memory block adjacent to the plurality of capacitor blocks, and wherein the plurality of capacitor blocks are disposed between the first memory block and the at least one dummy block (See Figure 1B)
With respect to claim 8, Higashitani discloses vertical memory structures [CA3/CA4] penetrating through the plurality of memory blocks; first vertical support structures penetrating through the plurality of capacitor blocks; and bit lines [BL] electrically connected to the vertical memory structures, wherein at least a portion of the plurality of capacitor blocks does not overlap the bit lines in the vertical direction (see ¶[0128] Figure 8).
With respect to claim 12, Higashitani discloses a signal path connecting the peripheral circuit structure to a capacitor block of the plurality of capacitor blocks (See Figure 29A).
Claim(s) 13-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yun et al. (U.S. Publication No. 2021/0143162 A1; hereinafter Yun).
With respect to claim 13, Yun discloses a semiconductor device, comprising: a first chip structure [110]; and a second chip structure vertically overlapping the first chip structure, wherein the first chip structure includes peripheral circuits [30], wherein the second chip structure includes: a stack structure [150]; a separation structure [151] penetrating through the stack structure; a plurality of contact plugs [THV]; and input/output pads (see ¶[0034]), wherein the stack structure includes a plurality of blocks spaced apart from each other, wherein each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction (see ¶[0081]), wherein the plurality of blocks include a plurality of memory blocks [MCR0/MCR1/MCR2] and a capacitor block [FR1/FR2], wherein the first and second chip structures further include a routing interconnection structure [116] between the peripheral circuits and the stack structure, wherein the plurality of contact plugs include a first input/output contact plug penetrating through the stack structure (see ¶[0129]), and the first input/output contact plug is electrically connected to a first input/output pad of the input/output pads, wherein the capacitor block includes a first capacitor electrode and second capacitor electrode, the first capacitor electrode including a plurality of first conductive layers among the conductive layers, and the second capacitor electrode including a plurality of second conductive layers among the conductive layers, and wherein the first capacitor electrode is electrically connected to the first input/output pad through the first input/output contact plug and the routing interconnection structure (See ¶[0148], ¶[0153] and Figure 3, 5B, 10C).
With respect to claim 14, Yun discloses wherein the second capacitor electrode is grounded to a ground region of the first chip structure through the routing interconnection structure (see ¶[0055]).
With respect to claim 15, Yun discloses wherein the routing interconnection structure of the first chip structure includes a lower interconnection structure [116], the lower interconnection structure including lower vertical portions disposed on different levels and lower horizontal portions disposed on different levels, wherein the routing interconnection structure of the second chip structure includes an upper interconnection structure [B1/TH_L], the upper interconnection structure including upper vertical portions disposed on different levels and upper horizontal portions disposed on different levels, and wherein at least one of the lower and upper horizontal portions of the routing interconnection structure is included in a capacitor routing interconnection electrically connecting the first capacitor electrode to the first input/output pad (See ¶[0148], ¶[0153])
With respect to claim 16, Yun discloses wherein the plurality of contact plugs include, first capacitor contact plugs [THV1] connected to the plurality of first conductive layers [EP1 through EP7] included in the first capacitor electrode, and second capacitor contact plugs connected to the plurality of second conductive layers included in the second capacitor electrode; and wherein the routing interconnection structure of the second chip structure further includes, a first capacitor interconnection electrically connecting the first capacitor contact plugs to each other, and a second capacitor interconnection electrically connecting the second capacitor contact plugs to each other (see ¶[0131] and ¶[0148]).
With respect to claim 17, Yun discloses wherein the routing interconnection structure of the first chip structure further includes lower bonding pads on the lower interconnection structure, and wherein the routing interconnection structure of the second chip structure further includes upper bonding pads, the upper bonding pads disposed below the upper interconnection structure and bonded to the lower bonding pads (See ¶[0061] and ¶[0128]).
With respect to claim 18, Yun discloses wherein the separation structure surrounds a side surface of the capacitor block, and wherein a block adjacent to the capacitor block of the plurality of blocks are spaced apart from the capacitor block by the separation structure (See Figure 5B).
With respect to claim 19, Yun discloses a data storage system, comprising: a semiconductor device including an input/output pad (see ¶[0034]); and a controller [37] electrically connected to the semiconductor device through the input/output pad and controlling the semiconductor device [20], wherein the semiconductor device further includes: a peripheral circuit structure [110]; a stack structure [150] vertically overlapping the peripheral circuit structure; and a separation structure [151] (see Figure 7) penetrating through the stack structure, wherein the stack structure includes a plurality of blocks spaced apart from each other by the separation structure, wherein each of the plurality of blocks include insulating layers and conductive layers alternately stacked in a vertical direction (see ¶[0081]), wherein the plurality of blocks include first blocks [MCR0/MCR1/MCR2] and a plurality of capacitor blocks [FR1/FR2] disposed between first blocks adjacent to each other among the first blocks, and wherein the plurality of capacitor blocks are spaced apart from each other by the separation structure (see Figure 5B).
With respect to claim 20, Yun discloses wherein each of the plurality of capacitor blocks includes a capacitor, wherein the capacitor includes capacitor electrodes including the conductive layers and capacitor dielectric layers including the insulating layers, and wherein a side surface of at least one capacitor block of the plurality of capacitor blocks is surrounded by the separation structure (See ¶[0148], ¶[0153] and Figure 5B, 10C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Higashitani in view of Yun.
With respect to claim 9, Higashitani fails to explicitly wherein the plurality of memory blocks include a plurality of first memory blocks and a plurality of second memory blocks, and wherein the plurality of capacitor blocks are disposed between the plurality of first memory blocks and the plurality of second memory blocks. In the same field of endeavor, Yun teaches a plurality of first memory blocks and a plurality of second memory blocks [MCR0/MCR1/MCR2], and wherein the plurality of capacitor blocks [FR1/FR2] are disposed between the plurality of first memory blocks and the plurality of second memory blocks (See Figure 5B).
Implementation of alternating memory blocks and capacitor blocks as taught by Yun allows for exclusive utilization of the capacitor for the memory cell regions (see Yun ¶[0077-0078]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 10, the combination of Higashitani and Yun discloses vertical memory structures [CA3/CA4] penetrating through the memory blocks; and bit lines [BL] electrically connected to the vertical memory structures, wherein at least one of the plurality of capacitor blocks overlaps the bit lines in the vertical direction (see Yun Figure 8 and Higashitani Figure 8).
With respect to claim 11, Higashitani fails to disclose wherein each of the first blocks extends in a first direction, wherein the plurality of capacitor blocks are disposed between first blocks adjacent to each other in a second direction perpendicular to the first direction, and wherein the plurality of capacitor blocks are spaced apart from each other in the second direction. In the same field of endeavor, Yun teaches wherein each of the first blocks extends in a first direction, wherein the plurality of capacitor blocks [FR1/FR2] are disposed between first blocks [MCR0/MCR1/MCR2] adjacent to each other in a second direction perpendicular to the first direction, and wherein the plurality of capacitor blocks are spaced apart from each other in the second direction (See Figure 5B).
Implementation of alternating memory blocks and capacitor blocks as taught by Yun allows for exclusive utilization of the capacitor for the memory cell regions (see Yun ¶[0077-0078]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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