DETAILED ACTION
This Office Action is in response to the applicant's application filed March 20th, 2024. In virtue of this communication, claims 1-23 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 2-6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the second surface of the wafer cap" in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation is understood to be --the fourth surface of the wafer cap--. Claims 3-5 are also rejected as they depend from claim 2.
Claim 5 recites the limitation “the second surface of the wafer cap” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation is understood to be --the fourth surface of the wafer cap--.
Claim 6 recites the limitation “the second surface of the wafer cap” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation is understood to be --a second surface of the wafer cap--.
Claim 8 recites the limitation “the second surface of the die” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation is understood to be --a second surface of the die--.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6, 7, 10, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yamagata et al. (US 2024/0387436 A1; hereinafter Yamagata).
With respect to claim 1, Yamagata teaches an apparatus 100 in at least Figs. 1-3, comprising:
a substrate 1 having opposing first 1a and second (bottom of 1 in Fig. 2) surfaces (see Figs. 1, 2, and paragraphs 28, 30);
an on-substrate device 3 on the first surface 1a of the substrate 1 (see Figs. 1, 2, and paragraphs 2, 34);
a wafer cap 2 on the first surface 1a of the substrate 1 over the on-substrate device 3 (see Figs. 1, 2, and paragraphs 28-31, 33, 34); and
a peripheral ring layer of a fusible alloy 33 configured to hermetically seal the wafer cap 2 to the first surface 1a of the substrate 1 around the on-substrate device 3 (see Figs. 1, 2, and paragraphs 30-33, 42).
With respect to claim 6, Yamagata teaches the apparatus of claim 1, wherein the wafer cap 2 further comprises a standoff ring 32 extending outwardly from a second surface of the wafer cap 2 along a periphery thereof to terminate in a distal end of the standoff ring 32, the fusible alloy 33 being interposed between the distal end of the standoff ring 32 and the first surface 1a of the substrate 1 (see Figs. 1, 2, and paragraphs 30-32).
With respect to claim 7, Yamagata teaches the apparatus of claim 1, wherein the substrate 1 further comprises a peripheral layer 31 of metal material on the first surface 1a of the substrate 1 spaced from and surrounding the on-substrate device 3, the fusible alloy being coextensive with and joined to the peripheral layer 31 of metal material to hermetically seal the wafer cap 2 around the on-substrate device 3 (see Figs. 1, 2, and paragraphs 30-34).
With respect to claim 10, Yamagata teaches a method of making an apparatus 100 in at least Figs. 1-3, comprising:
providing a substrate 1 that includes an on-substrate device 3 on a first surface 1a of the substrate 1 (see Figs. 1, 2, and paragraphs 2, 28, 30, 34);
placing a wafer cap 2 on the first surface 1a of the substrate 1 over the on-substrate device 3, in which the wafer cap 2 includes a continuous ring of a fusible alloy 33 on a respective surface of the wafer cap 2, and the ring of the fusible alloy 33 surrounds the on-substrate device 3 (see Figs, 1, 2, and paragraphs 28-31, 33, 34); and
reflowing the fusible alloy 33 to bond the respective surface of the wafer cap 2 to the first surface 1a of the substrate 1 and, after cooling, seal the wafer cap 2 around the on-substrate device 3 (see Figs. 1, 2, and paragraphs 30-33, 42).
With respect to claim 11, Yamagata teaches the method of claim 10, wherein: the substrate 1 further comprises a ring-shaped layer 31 of a metal material on the first surface 1a of the substrate 1 spaced from and surrounding the on-substrate device 3, the ring of fusible alloy 33 is coextensive with the layer of metal material (of 31), and reflowing the fusible alloy 33 includes forming an hermetic seal between the wafer cap 2 and the substrate 1 around the on-substrate device 3 (see Figs. 1, 2, and paragraphs 30-34, 42).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Yamagata et al. (US 2024/0387436 A1; hereinafter Yamagata) in view of Potter (US 2009/0151972 A1).
With respect to claim 2, Yamagata discloses the apparatus of claim 1, wherein the wafer cap 2 has opposing third (top of 2 in Fig. 2) and fourth (bottom of 2 in Fig. 2) surfaces, and the fourth surface (bottom of 2 in Fig. 2) of the wafer cap 2 is joined to the first surface 1a of the substrate 1, and the wafer cap 2 further comprises: a supporting layer 32 of material on the fourth surface (bottom of 2 in Fig. 2) of the wafer cap 2, in which the supporting layer 32 has a surface spaced apart from the fourth surface (bottom of 2 in Fig. 2) of the wafer cap 2 by a peripheral edge of the supporting layer 32 (see Figs. 1, 2, and paragraphs 30-32).
Yamagata does not disclose a channel in the supporting layer spaced inwardly from the peripheral edge along a periphery of the wafer cap.
Potter discloses an apparatus in Figs. 6a-7 comprising a channel 665 in a supporting layer 675 spaced inwardly from a peripheral edge along a periphery of a wafer cap 610 (see Figs. 6A-7 and paragraphs 64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the apparatus of Yamagata to include a channel in the supporting layer spaced inwardly from the peripheral edge along a periphery of the wafer cap as taught by Potter so the apparatus will have sufficient strength to maintain the force required to keep the package and base hermetically sealed after the compressive force is removed (see Potter: paragraph 33).
With respect to claim 4, the combination of Yamagata and Potter discloses the apparatus of claim 2, wherein at least a portion of the fusible alloy resides in the channel 665 (see Potter: Figs. 6a-7, paragraph 64. See Yamagata: paragraphs 30-33, 42 for fusible alloy).
Claims 8, 9, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamagata et al. (US 2024/0387436 A1; hereinafter Yamagata) in view of Takemura (US 2014/0131853 A1).
With respect to claim 8, Yamagata discloses the apparatus of claim 1.
Yamagata does not explicitly disclose wherein the substrate is a die and the apparatus further comprises: a leadframe having a die-attach surface area, a second surface of the die attached to the die-attach surface area of the leadframe; and a mold compound encapsulating the die, the wafer cap and at least a portion of the leadframe.
Takemura discloses an apparatus in at least Figs. 1A-1C wherein a substrate 2 is a die and the apparatus further comprises: a leadframe (of mother board) having a die-attach surface area, a second surface of the die attached to the die-attach surface area of the leadframe (of mother board); and a mold compound 4 encapsulating the die 2, the wafer cap 10 and at least a portion of the leadframe (of mother board) (see Figs. 1A-1C and paragraphs 51-55; 4 at least overlaps to cover underlying mother board).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the substrate of Yamagata would be a die and the apparatus of Yamagata further comprises: a leadframe having a die-attach surface area, a second surface of the die attached to the die-attach surface area of the leadframe; and a mold compound encapsulating the die, the wafer cap and at least a portion of the leadframe as taught by Takemura because it is well known in the art such apparatuses are externally connected and that mold compound is used to protect from the external environment (see Takemura: paragraph 55. Also see MPEP 2144 I).
With respect to claim 9, Yamagata discloses the apparatus of claim 1.
Yamagata does not disclose wherein the on-substrate device comprises a bulk acoustic wave device. It is noted that the on-substrate device of Yamagata is a MEMS device (see paragraph 2).
Takemura discloses an apparatus in at least Fig. 1C wherein an on-substrate device comprises a bulk acoustic wave device (see Fig. 1C and paragraphs 2, 4, 102).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the on-substrate device of Yamagata would comprise a bulk acoustic wave device as taught by Takemura because bulk acoustic wave devices are well known in the art. Electronic components in which functional elements, such as surface acoustic wave (SAW) filter elements, bulk acoustic wave (BAW) filter elements, micro-electro-mechanical systems (MEMS) elements, and switch ICs, are disposed on first principal surfaces of element substrates have become popular in recent years (see Takemura: paragraph 4). The apparatus of Yamagata would perform equally well with the on-substrate device substituted for the bulk acoustic wave device of Takemura and the results would have been predictable (see MPEP 2143 I B).
With respect to claim 17, Yamagata discloses the method of claim 10.
Yamagata does not explicitly disclose wherein the substrate is a die containing the on-substrate device, and the method further comprises: attaching a second side of the die to a leadframe; and encapsulating the die, the wafer cap and at least a portion of the leadframe within a mold compound.
Takemura discloses a method in at least Figs. 1A-1C wherein a substrate 2 is a die containing the on-substrate device, and the method further comprises: attaching a second side of the die to a leadframe (of mother board); and encapsulating the die 2, the wafer cap 10 and at least a portion of the leadframe (of mother board) within a mold compound 4 (see Figs. 1A-1C and paragraphs 51-55; 4 at least overlaps to cover underlying mother board).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the substrate of Yamagata would be a die containing the on-substrate device, and the method would further comprise: attaching a second side of the die to a leadframe; and encapsulating the die, the wafer cap and at least a portion of the leadframe within a mold compound as taught by Takemura because it is well known in the art such apparatuses are externally connected and that mold compound is used to protect from the external environment (see Takemura: paragraph 55. Also see MPEP 2144 I).
With respect to claim 18, Yamagata discloses the method of claim 10.
Yamagata does not disclose wherein the on-substrate device comprises a bulk acoustic wave device. It is noted that the on-substrate device of Yamagata is a MEMS device (see paragraph 2).
Takemura discloses a method in at least Fig. 1C wherein an on-substrate device comprises a bulk acoustic wave device (see Fig. 1C and paragraphs 2, 4, 102).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the on-substrate device of Yamagata would comprise a bulk acoustic wave device as taught by Takemura because bulk acoustic wave devices are well known in the art. Electronic components in which functional elements, such as surface acoustic wave (SAW) filter elements, bulk acoustic wave (BAW) filter elements, micro-electro-mechanical systems (MEMS) elements, and switch ICs, are disposed on first principal surfaces of element substrates have become popular in recent years (see Takemura: paragraph 4). The apparatus of Yamagata would perform equally well with the on-substrate device substituted for the bulk acoustic wave device of Takemura and the results would have been predictable (see MPEP 2143 I B).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamagata et al. (US 2024/0387436 A1; hereinafter Yamagata) in view of Chung (US 6,428,650 B1).
With respect to claim 12, Yamagata discloses the method of claim 10, wherein the substrate 1 is a first substrate, the wafer cap 2 is a first wafer cap (see Figs. 1, 2, and paragraphs 2, 28-31, 33, 34).
Yamagata does not explicitly disclose that prior to placing the first wafer cap on the first substrate, the method comprises: forming a plurality of instances of the continuous ring of the fusible alloy at respective locations distributed across a first surface of a second substrate; and singulating wafer caps from the second substrate to provide at least the first wafer cap.
Chung discloses a method in at least Figs. 3 and 4 wherein prior to placing a first wafer cap 140 on a first substrate 150, the method comprises: forming a plurality of instances of the continuous ring of a fusible alloy 130 at respective locations distributed across a first surface of a second substrate 132; and singulating wafer caps 140 from the second substrate 132 to provide at least the first wafer cap 140 (see Figs. 3, 4, column 5, line 31-47, column 7, line 46 - column 8, line 54, and column 11, line 62 - column 12, line 12; note 130 is electrically conductive thermoplastic adhesive filled with silver particles; 130 melt flows)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that prior to placing the first wafer cap on the first substrate in Yamagata, the method would comprise: forming a plurality of instances of the continuous ring of the fusible alloy at respective locations distributed across a first surface of a second substrate; and singulating wafer caps from the second substrate to provide at least the first wafer cap as taught by Yamagata so as produce multiple apparatus at the same time to improve productivity (see MPEP 2144 I).
With respect to claim 13, the combination of Yamagata and Chung discloses the method of claim 12, wherein: adjacent pairs of instances of the continuous ring are spaced apart from each other by an area of on the first surface of the second substrate that includes a portion of a saw street 134 that extends across the second substrate 132 between respective adjacent pairs of the instances of the continuous ring 130, and singulating wafer caps 140 comprises sawing through respective saw streets of the second substrate 132 with a mechanical saw to provide at least the first wafer cap 140 (see Chung: Figs. 3, 4, and column 5, line 31-47, column 7, line 63 - column 8, line 24, column 8, line 31-54, and column 11, line 62 - column 12, line 12; note 130 is electrically conductive thermoplastic adhesive filled with silver particles; 130 melt flows).
Claims 19, 20, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 6,428,650 B1) in view of Potter (2009/0151972 A1).
With respect to claim 19, Chung discloses a method in at least Figs. 3 and 4, comprising:
forming a plurality of instances of a continuous ring of die attach material 130 at respective locations distributed across a first surface of a substrate 132, in which adjacent pairs of the instances of the continuous ring are spaced apart from each other by an area of on the first surface that includes a portion of a saw street 134 that extends across the substrate 132 between respective adjacent pairs of the instances of the continuous ring (see Fig. 3 and column 7, line 46 - column 8, line 3); and
sawing through respective saw streets 134 of the substrate 132 to singulate wafer caps 140 from the substrate 132, in which each of the singulated wafer caps 140 includes a respective instance of the continuous ring of die attach material 130 on the first surface thereof (see Figs. 3, 4, and column 7, line 46 - column 8, line 30).
Chung does not explicitly disclose wherein the substrate is a silicon substrate.
Potter discloses a method wherein a substrate is a silicon substrate (silicon cap) (see Fig. 3 and paragraph 53; note silicon used for cap; equivalent to claimed wafer cap).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the substrate of Chung would be a silicon substrate as taught by Potter because silicon substrates are well known in the art and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
With respect to claim 20, the combination of Chung and Potter discloses the method of claim 19, wherein the die attach material 130 comprises a fusible alloy and sawing through the saw streets 134 comprises sawing through substrate 132 with a mechanical saw to provide the singulated wafer caps 140 (see Chung: Figs. 3, 4, and column 5, line 31-47, column 7, line 63 - column 8, line 24, column 8, line 31-54, and column 11, line 62 - column 12, line 12; note 130 is electrically conductive thermoplastic adhesive filled with silver particles; 130 melt flows).
With respect to claim 23, the combination of Chung and Potter discloses a wafer cap 140 produced according to the method of claim 20 (see Chung and the rejection of claims 19 and 20 above).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 6,428,650 B1) in view of Potter (2009/0151972 A1) as applied to claim 20 above, and further in view of Takemura (US 2014/0131853 A1).
With respect to claim 22, the combination of Chung and Potter discloses the method of claim 20, further comprising: providing a die 150 that includes an on-substrate device 160 on a first side of the die 160; placing a respective one of the wafer caps 140 on the first side of the die 150 over the on-substrate device 160, such that the continuous ring of the fusible alloy (of 130) thereof surrounds the on-substrate device 160 on the first side of the die 150; reflowing the fusible alloy (of 130) to bond the respective one of the wafer caps 140 to the first side of the die 150 and, after cooling, seal the respective one of the wafer caps 140 around the on-substrate device 160 (see Chung: Figs. 3, 4, and column 5, line 31-47, column 7, line 63 - column 8, line 24, column 8, line 31-54, and column 11, line 62 - column 12, line 12; note 130 is electrically conductive thermoplastic adhesive filled with silver particles; 130 melt flows then cools to seal).
The combination does not disclose attaching a second side of the die to a leadframe; and encapsulating the die, the respective one of the wafer caps and at least a portion of the leadframe within a mold compound.
Takemura discloses a method in at least Figs. 1A-1C comprising attaching a second side of a die 2 to a leadframe (of mother board); and encapsulating the die 2, the respective one of the wafer caps 10 and at least a portion of the leadframe (of mother board) within a mold compound 4 (see Figs. 1A-1C and paragraphs 51-55; 4 at least overlaps to cover underlying mother board).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method of Chung and Potter would further comprise attaching a second side of the die to a leadframe; and encapsulating the die, the respective one of the wafer caps and at least a portion of the leadframe within a mold compound as taught by Takemura because it is well known in the art such apparatuses are externally connected and that mold compound is used to protect from the external environment (see Takemura: paragraph 55. Also see MPEP 2144 I).
Allowable Subject Matter
Claims 3, 5, 14-16, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest:
wherein the supporting layer comprises a polyimide, as called for in claim 3 (pending correction of the 112 rejection above);
wherein the wafer cap further comprises: a standoff ring in the channel extending outwardly from the fourth surface of the wafer cap beyond the surface of the supporting layer to terminate in a distal end of the standoff ring, the fusible alloy being interposed between the distal end of the standoff r0ing and the first surface of the substrate, as called for in claim 5 (pending correction of the 112 rejection above);
wherein forming the plurality of instances of the ring of fusible alloy comprises: forming a patterned layer of photoresist on the first surface of the second substrate having recesses extending though the patterned layer of photoresist to the first surface of the second substrate, in which the recesses are arranged and configured to be coterminous with the respective locations; plating the fusible alloy in the recesses and on the first surface of the second substrate; removing the patterned layer of photoresist from the first surface of the second substrate; and reflowing the fusible alloy to form respective instances of the ring of fusible alloy on the first surface of the second substrate, as called for in claim 14;.
wherein prior to singulating wafer caps, the method comprises: forming a supporting layer of a polymer material on the first surface of the second substrate, in which the supporting layer extends from the first surface of the second substrate to terminate in a surface thereof; and forming respective channels in the supporting layer, each respective channel being arranged and configured to be coterminous with the respective locations, as called for in claim 15 (claim 16 depends from claim 15); and
wherein prior to sawing through the saw streets, the method comprises: forming a plurality of supporting rings of a polymer material on the first surface of the substrate at the respective locations; and forming respective channels in each supporting ring, in which each respective channel is arranged and configured to define the respective locations, such that each of the plurality of instances of the continuous ring of die attach material is coterminous with and formed within a respective channel, as called for in claim 21.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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