DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 7, 16 and 20 have been cancelled; claims 1, 9, and 17 have been amended; claims 21-23 have been newly added; and claims 1-6, 8-15, 17-19 and 21-23 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8, 9, 10, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2022/0020688 A1, hereinafter “Xie”) in view of Yu et al. (US 2007/0278681 A1, hereinafter “Yu”).
In regards to claim 1, Xie discloses (See, for example, Figs. 1-5) a semiconductor structure comprising:
a metal structure which spans vertically across a M1 metal line (Mx-1) level and a V1 via
level (Vx-1) above the M1 metal line level (Mx-1), wherein the metal structure comprises
both a metal line in the M1 metal line level (Mx-1) and a via in the V1 via level (Vx-1), wherein
an individual metal grain (“the lower metal Mx-1 202 and the via Vx-1 204 are patterned from the same metal layer and thus are continuous structures without any interface”, See for example, Par [0028]) of the metal structure spans from the metal line in the M1 metal line
level (Mx-1) to the via in the V1 via level (Vx-1).
Xie fails to explicitly teach wherein a width of a bottommost horizontal surface of the via in the V1 via level is greater than a width of a topmost horizontal surface of the metal line in the M1 metal line level.
Yu while disclosing an interconnection structure teaches (See, for example, Figs. 2B, 3B and 8-10) wherein a width (R ) of a bottommost horizontal surface of the via (22) in the V1 via level is greater than a width (Wm-1) of a topmost horizontal surface of the metal line in the
M1 metal line level (M-1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Xie such that the bottommost surface of the via is wider than the topmost surface of the underlying metal line, as taught by Yu, because
narrowing the metal line relative to the via at a fixed pitch increases line spacing, which
reduces parasitic capacitance, RC delay and leakage current.
In regards to claim 9, Xie discloses (See, for example, Figs. 1-5) a semiconductor structure comprising: a metal line in a M1 metal line level (Mx-1); and
a via in a V1 via level (Vx-1) above the M1 metal line level (Mx-1),
wherein the metal line and the via form one continuous metal structure grain (“the lower metal Mx-1 202 and the via Vx-1 204 are patterned from the same metal layer and thus are continuous structures without any interface”, See for example, Par [0028]).
Xie fails to explicitly teach wherein a width of a bottommost horizontal surface of the via in the V1 via level is greater than a width of a topmost horizontal surface of the metal line in the M1 metal line level.
Yu while disclosing an interconnection structure teaches (See, for example, Figs. 2B, 3B and 8-10) wherein a width (R ) of a bottommost horizontal surface of the via (22) in the V1 via level is greater than a width (Wm-1) of a topmost horizontal surface of the metal line in the
M1 metal line level (M-1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Xie such that the bottommost surface of the via is wider than the topmost surface of the underlying metal line, as taught by Yu, because
narrowing the metal line relative to the via at a fixed pitch increases line spacing, which
reduces parasitic capacitance, RC delay and leakage current.
In regards to claim 17, Xie discloses (See, for example, Figs. 1-5) a semiconductor structure comprising: a metal line in a M1 metal line level (Mx-1); and
a set of vias in a V1 via level (Vx-1, “at least one via Vx-1”, See Abstract; “lower vias Vx-1”, See Par [0027]) above the M1 metal line level (Mx-1),
wherein the metal line and the set of vias are one continuous metal structure grain (“the lower metal Mx-1 202 and the via Vx-1 204 are patterned from the same metal layer and thus are continuous structures without any interface”, See for example, Par [0028]).
Xie fails to explicitly teach wherein a width of a bottommost horizontal surface of the via in the V1 via level is greater than a width of a topmost horizontal surface of the metal line in the M1 metal line level.
Yu while disclosing an interconnection structure teaches (See, for example, Figs. 2B, 3B and 8-10) wherein a width (R ) of a bottommost horizontal surface of the via (22) in the V1 via level is greater than a width (Wm-1) of a topmost horizontal surface of the metal line in the
M1 metal line level (M-1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Xie such that the bottommost surface of the via is wider than the topmost surface of the underlying metal line, as taught by Yu, because
narrowing the metal line relative to the via at a fixed pitch increases line spacing, which
reduces parasitic capacitance, RC delay and leakage current.
In regards to claim 6, Xie discloses (See, for example, Figs. 1-5) the metal structure comprises a second via in the V2 via level (VX, See for example, Fig. 5A).
In regards to claim 8, Xie discloses (See, for example, Figs. 1-5) a second metal line in a M3 metal line layer above the V2 via level, connected to the via (“a subsequent subtractive etch
during patterning of the next level of metal lines Mx+1 (not shown) can be used in the same manner as described above to self-align the upper via Vx 504…”, See Par [0041]) .
In regards to claim 10, Xie discloses (See, for example, Figs. 1-5) a second metal line in a M2 metal line layer (Mx) above the V1 via level (Vx-1), connected to the via (See, for example, Fig. 5A).
In regards to claim 15, Xie discloses (see, for example, Figs. 1-5) a second via (“lower vias Vx-1”, See Par [0027]) in the V1 via level (Vx-1).
Claims 2-5, 11-14, 18-19, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of YU as applied to claim 1, 9 and 18, and further in view of Murray et al. (US 2023/0013937 A1, hereinafter “Murray”).
In regards to claims 2, 11 and 18, Xie discloses all limitations of claims 1, 9 and 17 above except that an inter-level dielectric surrounding the metal line; and a barrier layer separating a lower horizontal surface and vertical side surfaces of the metal line of the metal structure from the inter-layer dielectric.
Murray while disclosing a semiconductor device teaches (See, for example, Figs. 1-2) an inter-level dielectric (204) surrounding the metal line (208); and a barrier layer (206) separating a lower horizontal surface and vertical side surfaces of the metal line (208) of the metal structure from the inter-layer dielectric (204).
In regards to claims 3 and 12, Xie as modified above discloses (See, for example, Figs. 3B-3C, Murray) a dielectric cap (314) on an upper horizontal surface of the inter-layer dielectric (204).
In regards to claims 4 and 5, Xie as modified above discloses (See, for example, Fig. 1) a lower horizontal surface of the via (110) covers a portion of an upper horizontal surface of the inter-level dielectric (204) surrounding the metal line (208).
In regards to claim 13, Xie as modified above discloses (See, for example, Figs. 1-2, Murray) a lower horizontal surface of the via (110) covers a portion of an upper horizontal surface of the inter-level dielectric (204).
In regards to claim 14, Xie as modified above discloses (See, for example, Figs. 1-2, Murray) a first lower horizontal surface (lower surface of 206 surrounding 208) of the barrier layer (206) covers a portion of an upper horizontal surface (the surface of 204 right under 206 and under 208) of the inter-level dielectric (204).
In regards to claim 19, Xie as modified above discloses (See, for example, Figs. 1-2, Murray) a lower horizontal surface of each of the vias (110) of the set of vias covers a portion of an upper horizontal surface of the inter-level dielectric (204).
In regards to claim 21-23, Xie as modified above discloses (See, for example, Figs. 1-2, Murray) that the barrier layer (206, Murray) is located between a portion of the via (110, Murray) in the V1 via level and a portion of the inter-level dielectric (204) surrounding the metal line in the M1 metal line level (208).
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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