Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/2024 and 06/17/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim1 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for “ A semiconductor device comprising: a circuit device including a transistor, wherein the transistor includes a first source/drain region, a second source/drain region, a channel region and a gate; a front side interconnection structure including a plurality of front side interconnection layers on different levels from each other, wherein front side interconnection structure is at a higher level than the transistor; a first back side interconnection structure and a second back side interconnection structure, wherein the first and second back side interconnection structures are at a lower level than the transistor; a first through-electrode on the first back side interconnection structure”, does not reasonably provide enablement for “a second through-electrode on the first back side interconnection structure” The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
Please note while the specification is enabled for a second through-electrode [79] on the second back side interconnection structure [81-2], it is not enabled for a second through-electrode [79] on the first back side interconnection structure[81-1]”
Claims 2-20 are also rejected under 112 based on their dependance on independent claim1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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