Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 and 15-20 in the reply filed on 6/30/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (20140138851)
Regarding claim 1, Kim teaches a semiconductor package (fig. 28), comprising:
a printed circuit board (PCB) (fig. 28: 101; par. 57);
a first stack of semiconductor dies having a first circuitry layout (please see 10a/10b die stack on the left);
a second stack of semiconductor dies adjacent the first stack of semiconductor dies and having a second circuitry layout that is symmetrical to the first circuitry layout (please see 10a/10b die stack on the right); and
a plurality of contacts (BC2 and BC1) provided between the first stack of semiconductor dies and the second stack of semiconductor dies,
wherein a first subset of the plurality of contacts are electrically coupled to the first stack of semiconductor dies and a second subset of the plurality of contacts are electrically coupled to the second stack of semiconductor dies (please see top down view in, for example fig. 7, which shows multiple BC1 and BC2 being coupled to the dies).
Regarding claim 2, Kim teaches a semiconductor package of claim 1, wherein the first stack of semiconductor dies and the second stack of semiconductor dies are associated with a single channel (please IC each stack associated with a single channel, “IC”).
Regarding claim 3, Kim teaches a semiconductor package of claim 1, wherein the first stack of semiconductor dies is associated with a first channel and the second stack of semiconductor dies is associated with a second channel (please see each BC1 and BC2 have their respective IC channel).
Regarding claim 4, Kim teaches a semiconductor package of claim 1, further comprising an integrated circuit electrically coupled to the PCB (please see IC within element 200, which is connect to 101).
Regarding claim 5, Kim teaches a semiconductor package of claim 4, further comprising a trace extending from the integrated circuit to at least one of a first contact in the first subset of the plurality of contacts and a first contact in the second subset of the plurality of contacts (please see IC within element 200, which is connect to 101 and thus BC2 and BC1).
Regarding claim 6, Kim teaches a semiconductor package of claim 1, wherein a first contact in the first subset of the plurality of contacts is electrically coupled to a first contact in the second subset of the plurality of contacts (please see fig. 28 which shows these elements being physically and electrically connected).
Regarding claim 7, this claim uses language directed towards the process of forming the device structure. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. Case law makes it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language only requires the device structure, which does not distinguish the invention from prior art Kim, who teaches the structure as claimed, as show in independent claim 1.
Regarding claim 8, Kim teaches a semiconductor package of claim 1, wherein the first stack of semiconductor dies is a stack of NAND memory dies (par. 38).
Regarding claim 15, Kim teaches a semiconductor package (fig. 28), comprising:
a printed circuit board (PCB) (101);
a first stack of semiconductor dies having a first plurality of connection means associated with a first layout (please see 10a/10b die stack on the left);
a second stack of semiconductor dies adjacent the first stack of semiconductor dies and having a second plurality of connection means associated with a second layout that is symmetrical to the first layout (please see 10a/10b die stack on the right);
a plurality of contact means (BC2 and BC1) provided between the first stack of semiconductor dies and the second stack of semiconductor dies;
a first plurality of transmission means (IC connected to BC2) electrically coupling the first plurality of connection means to a first subset of contact means of the plurality of contact means; and
a second plurality of transmission means (IC connected to BC1) electrically coupling the second plurality of connection means to a second subset of contact means of the plurality of contact means.
Regarding claim 16, Kim teaches a semiconductor package of claim 15, wherein the first stack of semiconductor dies and the second stack of semiconductor dies are associated with a single channel means (please IC each stack associated with a single channel, “IC”).
Regarding claim 17, Kim teaches a semiconductor package of claim 15, wherein the first stack of semiconductor dies is associated with a first channel means and the second stack of semiconductor dies is associated with a second channel means (please IC each stack associated with a single channel, “IC”).
Regarding claim 18, Kim teaches a semiconductor package of claim 15, further comprising a communication means extending from an integrated circuit to at least one contact means of the plurality of contact means (please see IC within element 200, which is connect to 101).
Regarding claim 19, Kim teaches a semiconductor package of claim 15, wherein a first contact means in the first subset of contact means is electrically coupled to a first contact means in the second subset of contact means (please see IC within element 200, which is connect to 101 and thus BC2 and BC1).
Regarding claim 20, this claim uses language directed towards the process of forming the device structure. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. Case law makes it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language only requires the device structure, which does not distinguish the invention from prior art Kim, who teaches the structure as claimed, as show in independent claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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