DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant's election with traverse of Species I and claims 1-2 and 4-16 in the reply filed on July 07, 2026 is acknowledged. The traversal is on the ground(s) that “there is a substantial overlap of common elements…of the alleged Species I and Species II.” This is found persuasive and all claims are under examination and the Election of Species Requirement on June 30, 2026 is hereby withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 1, it is not clear whether limitations are missing in view of “the second word line, , the second active pattern” . Thus, the limitation renders the claims indefinite and clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2022/0102352 A1 to Lee et al. (“Lee”). As to claim 1, Lee discloses a semiconductor memory device, comprising: a peripheral gate structure (SA, NMOS, PMOS) on a substrate (100); bit lines (BL) above the peripheral gate structure (SA, NMOS, PMOS), the bit lines (BL) being spaced apart from each other in a first direction, the bit lines (BL) extending in a second direction different from the first direction; a first active pattern (VP1) and a second active pattern (VP2) above the bit lines (BL), the first active pattern (VP1) and the second active pattern (VP2) being spaced apart from each other in the second direction; a first word line (GE1a) and a second word line (GE2a) between the first active pattern (VP1) and the second active pattern (VP2), the first word line (GE1a) being adjacent to the first active pattern (VP1), the second word line (GE2a) being adjacent to the second active pattern (VP2); a first back gate electrode (GE1b) corresponding to the first word line (GE1a), the first active pattern (VP1) being between the first back gate electrode (GE1b) and the first word line (GE1a); a second back gate electrode (GE2b) corresponding to the second word line (GE2a), , the second active pattern (VP2) being between the second back gate electrode (GE2b) and the second word line (GE2a); and a word line shielding structure (141, 150, SL2, LP) between the first word line (GE1a) and the second word line (GE2a) (See Fig. 1-Fig. 12, ¶ 0066-¶ 0076, ¶ 0079-¶ 0084, ¶ 0094-¶ 0096, ¶ 0106-¶ 0118, ¶ 0127-¶ 0129, ¶ 0190) (Notes: the limitation “word line shielding structure” is interpreted as a structure that covers or protects the word line). As to claim 2, Lee further discloses wherein an interval between the first word line (GE1a) and the second word line (GE2a) in the second direction is 10 nm or less (See ¶ 0083, ¶ 0084) (Notes: the first and second word lines may be 1 nm and formed of a multi-layered structure such that the outermost layer is an interval that is 10 nm or less).
As to claim 3, Lee further discloses wherein an interval between the first word line (GE1a) and the second word line (GE2a) in the second direction is 6 nm or less (See ¶ 0083, ¶ 0084) (Notes: the first and second word lines may be 1 nm and formed of a multi-layered structure such that the outermost layer is an interval that is 6 nm or less).
As to claim 4, Lee further discloses wherein the word line shielding structure (141, 150, SL2, LP) comprises: a word line shielding conductive pattern (SL2, LP); and a word line shielding insulating liner (141, 150) including a first portion between the word line shielding conductive pattern (SL2, LP) and the first word line (GE1a) and a second portion between the word line shielding conductive pattern (SL2, LP) and the second word line (GE2a) (See Fig. 12).
As to claim 5, Lee further discloses wherein a length of the word line shielding conductive pattern (SL2, LP) in the second direction is 2 nm or less (See Fig. 12) (Notes: the curvature toward the top and bottom is 2 nm or less).
As to claim 6, Lee further discloses wherein a length of the word line shielding insulating liner (141, 150) in the second direction is 2 nm or less (See Fig. 12) (Notes: the length corresponds to the first/second portion is 2 nm or less).
As to claim 7, Lee further discloses wherein the word line shielding conductive pattern (SL2, LP) includes a conductive material including conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a two-dimensional material, a metal, or a combination thereof (See ¶ 0106, ¶ 0109).
As to claim 8, Lee further discloses wherein the word line shielding insulating liner (141, 150) includes an insulating material including a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, a silicon carbide (SiC) film, a silicon carbon nitride (SiCN) film, or a combination thereof (See ¶ 0190).
As to claim 9, Lee further discloses wherein the word line shielding conductive pattern (SL2, LP) extends in a third direction different from the first direction and the second direction and overlaps the first word line (GE1a) and the second word line (GE2a) in the second direction (See Fig. 12).
As to claim 10, Lee further discloses wherein a length of the word line shielding conductive pattern (SL2, LP) in the third direction is equal to or greater than a length of each of the first word line (GE1a) and the second word line (GE2a) in the third direction (See Fig. 12).
As to claim 11, Lee further discloses wherein a height of a lower end portion of the word line shielding conductive pattern (SL2, LP) in the third direction is equal to or less than a height of a lower end portion of each of the first word line (GE1a) and the second word line (GE2a) in the third direction, and a height of an upper end portion of the word line shielding conductive pattern (SL2, LP) in the third direction is equal to or greater than a height of an upper end portion of each of the first word line (GE1a) and the second word line (GE2a) in the third direction (See Fig. 12).
As to claim 12, Lee further discloses wherein the word line shielding conductive pattern (SL2, LP) extends in the third direction and overlaps the first back gate electrode (GE1b) and the second back gate electrode (GE2b) in the second direction (See Fig. 12).
As to claim 13, Lee discloses further comprising: a bit line shielding structure (SL1, 110) being adjacent to an adjacent one of the bit lines (BL) and above the peripheral gate structure (SA, NMOS, PMOS), the bit line shielding structure (SL1) extending in the second direction (See Fig. 8, ¶ 0106, ¶ 0112).
As to claim 14, Lee further discloses wherein the bit line shielding structure (SL1, 110) includes a bit line shielding conductive pattern (SL1) and a bit line shielding insulating liner (110), the bit line shielding liner (110) being between the bit line shielding conductive pattern (SL1) and the bit line (BL) (See Fig. 8).
As to claim 15, Lee further discloses wherein each of the first active pattern (VP1) and the second active pattern (VP2) is made of a monocrystalline semiconductor material (See ¶ 0080).
As to claim 16, Lee discloses further comprising: a bonding insulating film (110) between the peripheral gate structure (SA, NMOS, PMOS) and the bit lines (BL) (See Fig. 10, ¶ 0112).
As to claim 17, Lee discloses a semiconductor memory device, comprising: a peripheral gate structure (SA, NMOS, PMOS) on a substrate (100); bit lines (BL) above the peripheral gate structure (SA, NMOS, PMOS), the bit lines (BL) being spaced apart from each other in a first direction, the bit lines (BL) extending in a second direction different from the first direction; a first active pattern (VP1) and a second active pattern (VP2) above the bit lines (BL), the first active pattern (VP1) and the second active pattern (VP2) being spaced apart from each other in the second direction; a first word line (GE1a) and a second word line (GE2a) between the first active pattern (VP1) and the second active pattern (VP2), the first word line (GE1a) being adjacent to the first active pattern (VP1), the second word line (GE2a) being adjacent to the second active pattern (VP2); a first back gate electrode (GE1b) corresponding to the first word line (GE1a), the first active pattern (VP1) being between the first back gate electrode (GE1b) and the first word line (GE1a); and a second back gate electrode (GE2b) corresponding to the second word line (GE2a), the second active pattern (VP2) being between the second back gate electrode (GE2b) and the second word line (GE2a), wherein an interval between the first word line (GE1a) and the second word line (GE2a) in the second direction is 6 nm or less (See Fig. 1-Fig. 12, ¶ 0066-¶ 0076, ¶ 0079-¶ 0084, ¶ 0094-¶ 0096, ¶ 0106-¶ 0118, ¶ 0127-¶ 0129, ¶ 0190) (Notes: the first and second word lines may be 1 nm and formed of a multi-layered structure such that the outermost layer is an interval that is 6 nm or less).
As to claim 18, Lee discloses further comprising: a word line shielding structure (141, 150, SL2, LP) between the first word line (GE1a) and the second word line (GE2a) (See Fig. 12) (Notes: the limitation “word line shielding structure” is interpreted as a structure that covers or protects the word line).
As to claim 19, Lee further discloses wherein the word line shielding structure (141, 150, SL2, LP) comprises, a word line shielding conductive pattern (SL2, LP), and a word line shielding insulating liner (141, 150) being between the word line shielding conductive pattern (SL2, LP) and the first word line (GE1a) and being between the word line shielding conductive pattern (SL2, LP) and the second word line (GE2a), and wherein the word line shielding conductive pattern (SL2, LP) extends in a third direction different from the first direction and the second direction, and overlaps the first word line (GE1a) and the second word line (GE2a) in the second direction (See Fig. 12).
As to claim 20, Lee discloses wherein a semiconductor memory device, comprising: a peripheral gate structure (SA, NMOS, PMOS) on a substrate (100); bit lines (BL) above the peripheral gate structure (SA, NMOS, PMOS), the bit lines (BL) being spaced apart from each other in a first direction, the bit lines (BL) extending in a second direction different from the first direction; a bit line shielding structure (SL1, 110) being adjacent to an adjacent one of the bit lines (BL) and above the peripheral gate structure (SA, NMOS, PMOS), the bit line shielding structure (SL1, 110) extending in the second direction; a first active pattern (VP1) and a second active pattern (VP2) above the bit lines (BL), the first active pattern (VP1) and the second active pattern (VP2) being spaced apart from each other in the second direction; a first word line (GE1a) and a second word line (GE2a) between the first active pattern (VP1) and the second active pattern (VP2), the first word line (GE1a) being adjacent to the first active pattern (VP1), the second word line (GE2a) being adjacent to the second active pattern (VP2); a first back gate electrode (GE1b) corresponding to the first word line (GE1a), the first active pattern (VP1) being between the first back gate electrode (GE1b) and the first word line (GE1a); a second back gate electrode (GE2b) corresponding to the second word line (GE2a), the second active pattern (VP2) being between the second back gate electrode (GE2b) and the second word line (GE2a); and a word line shielding structure (141, 150, SL2, LP) between the first word line (GE1a) and the second word line (GE2a), wherein an interval between the first word line (GE1a) and the second word line (GE2a) in the second direction is 6 nm or less (See Fig. 1-Fig. 12, ¶ 0066-¶ 0076, ¶ 0079-¶ 0084, ¶ 0094-¶ 0096, ¶ 0106-¶ 0118, ¶ 0127-¶ 0129, ¶ 0190) (Notes: the limitation “shielding structure” is interpreted as a structure that covers or protects the word line and the bit line and the first and second word lines may be 1 nm and formed of a multi-layered structure such that the outermost layer is an interval that is 6 nm or less).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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