Prosecution Insights
Last updated: October 01, 2026
Application No. 18/610,829

TRANSISTOR MANUFACTURING METHOD

Non-Final OA §112
Filed
Mar 20, 2024
Priority
Mar 27, 2023 — FR 2302895
Examiner
WOLDEGEORGIS, ERMIAS T
Art Unit
Tech Center
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
542 granted / 764 resolved
+10.9% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
42 currently pending
Career history
805
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
70.9%
+30.9% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 764 resolved cases

Office Action

§112
CTNF 18/610,829 CTNF 85098 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). Information Disclosure Statement The information disclosure statement filed on 3/20/2024 has been acknowledged and a signed copy of the PTO-1449 is attached herein. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: “SOI BIPOLAR TRANSISTOR WITH DUAL GATES OVER EMITTER-BASE AND COLLECTOR-BASE JUNCTIONS” . Claim Objections 07-29-01 AIA Claim 6 is objected to because of the following informalities: “an epitaxial region” in line 2, should be replaced by “an epitaxially grown layer/region” for clarity. Because, for example, in Par [0089] of the specification, the epitaxial growth (process) of a layer of semiconductor layer(s) (product) are described therein . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 07-34-05 AIA Claim 9 recites the limitation " the gate stack " in lines 2-3 . There is insufficient antecedent basis for this limitation in the claim. Allowable Subject Matter Claim 1 is allowed over prior art of record. 13-03 AIA The following is an examiner' s statement of reasons for allowance: In regards to claim 1, Jain et al. (US 2018/0175180 A1, hereinafter “Jain”) discloses a bipolar transistor (50), comprising: an insulating layer (BOX layer 14); a base region on the insulating layer doped with a first conductivity type (section 22); a second portion of an emitter region that is not doped and in contact with the base region (emitter 36); a second portion of a collector region that is not doped and in contact with the base region (section 20); and a first portion of the collector region doped with the second conductivity type (collector contact 40). However, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole. In particular, the prior art fails to teach or suggest: an emitter region on the insulating layer including a first portion doped with a second conductivity type and a second portion that is not doped; a first gate extending over the second portion of the emitter region and a first portion of the base region; and a second gate extending over the second portion of the collector region and a second portion of the base region. Specifically, while Jain discloses dummy gates (28, 30), the prior art fails to teach the specific structural arrangement of the first and second gates extending over the specifically claimed doped and undoped portions of the emitter, collector, and base regions. For these reasons, claim 1 is allowable over the prior art of record. Claims 2-16 are also allowed as being dependent of the allowed independent base claim . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893 Application/Control Number: 18/610,829 Page 2 Art Unit: 2893 Application/Control Number: 18/610,829 Page 3 Art Unit: 2893
Read full office action

Prosecution Timeline

Mar 20, 2024
Application Filed
May 01, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
83%
With Interview (+11.9%)
2y 10m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 764 resolved cases by this examiner. Grant probability derived from career allowance rate.

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