DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 7-9, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pauley et al., WO 2005/015564, hereafter “Pauley,” in view of CN 117690473 A, hereafter, “Li.”
With respect to claim 1, Pauley teaches a system, comprising:
a memory module, comprising:
a controller configured to generate a first signal (pars. 29-30, the controller provides a chip-select signal);
a first memory device having a first capacity (pars. 27-28 the memory module that is to be replaced); and
a serial presence detect (SPD) device configured to store data of the memory module (pars. 28, the SPD device); and
an SPD writer configured to change the data according to a capacity of the memory module (par. 28, the SPD Byte 5 is changed to the number of ranks corresponding to the new memory module), the SPD writer comprising:
a test pad configured to measure the first signal (pars. 29-30, the controller provides a chip-select signal to a memory, the BIOS code of the memory decoding (measuring) the chip-select signal received at the memory terminal (test pad). The memory controller is shown providing chip select signals to terminals of the memory in figures 1A and 5A),
wherein in response to the first memory device being replaced by a second memory device having a second capacity different from the first capacity, the test pad measures the first signal (par. 29, the BIOS code decodes the SPD Byte 5 from a chip-select signal (measures the first signal)).
Pauley fails to teach that the first signal is a bank signal, and verifying signal integrity.
Li teaches:
a test pad configured to measure the first bank signal, thereby verifying signal integrity (pars. 85-86, “S209, performing a signal integrity test on the sixth batch of memory banks within the first frequency range to obtain a seventh batch of memory banks, wherein the seventh batch of memory banks are memory banks having no failure and/or failure in the signal integrity test; wherein the signal integrity test comprises a signal quality test at the time of interference. The signal integrity test belongs to the selectable test item of the memory bank detection, the memory bank after the signal integrity test has the cost higher than the universal memory bank, and the signal integrity test will be applied to the abnormal memory bank analysis and the new product memory bank introduction process. The signal integrity test mainly detects the quality of the signal when the signal passes through the link so as to avoid the signal quality not reaching the standard due to the interference and impedance in the link.”)
It would have been obvious to one of ordinary skill in the art, having the teachings of Pauly and Li before him before the earliest effective filing date, to modify the memory system of Pauley with the memory system of Li, in order to perform the signal integrity test, which verifies whether signal quality is below standard due to interference and impedance in the link, as taught by Li in par. 86.
With respect to claim 3, Pauley and Li teach the limitations of the parent claim. Pauley further teaches the system of claim 1, wherein
the data further comprises a first data value corresponding to the first memory device (par. 28, the value is SPD byte 5, indicating the number of ranks of the memory module),
in response to the first memory device being replaced by the second memory device, the SPD writer changes the first data value to a second data value corresponding to the second memory device (pars. 29-30, the SPD byte 5 is changed and provided on a second chip-select signal),
Li teaches:
the SPD writer determines whether the first bank signal measured by the test pad is at a high voltage level during a period to verify signal integrity (pars. 85-86).
With respect to claim 4, Pauley and Li teach the limitations of the parent claim. Pauley further teaches the system of claim 3, wherein
the data further comprises a third data value corresponding to the first memory device (par. 28, total module capacity),
in response to the first memory device being replaced by the second memory device, the SPD writer changes the third data value to a fourth data value corresponding to the second memory device (par. 28, after SPD Byte 5 is changed, total module capacity is calculated by multiplying the content of SPD Byte 5 by SPD Byte 31).
With respect to claim 5, Pauley and Li teach the limitations of the parent claim. Pauley further teaches the system of claim 4, wherein
the first data value is equal to “02”, and the second data value is equal to “04” (par. 28, Table 1, right column Hex has a value of “02” for 2 ranks and a value of “04” for 4 ranks).
With respect to claim 7, Pauley and Li teach the limitations of the parent claim. Pauley further teaches the system of claim 3, wherein
the test pad is further configured to measure a second signal generated by the controller, wherein the second bank signal is different from the first signal (pars. 29-30, the second chip select signal),
in response to the first memory device being replaced by the second memory device, the test pad measures the second signal (pars. 29-30, the second chip select signal is received).
Li teaches the second signal is a bank signal, and the SPD writer determines whether the second bank signal is at the high voltage level during the period to verify signal integrity (pars. 82-83).
With respect to claim 8, Pauley and Li teach the limitations of the parent claim. Pauley further teaches the system of claim 7, wherein
the test pad is further configured to measure a chip select signal generated by the controller (pars. 29-30, where four chip select signals are used, the third chip select signal of four corresponding to the chip select signal),
in response to the first memory device being replaced by the second memory device, the test pad measures the chip select signal, and the SPD writer determines whether the chip select signal at low voltage level during the period (pars. 29-30, the third chip select signal is received).
Li teaches verifying signal integrity (pars. 82-83).
With respect to claim 9, Pauley teaches a method for operating a memory system, comprising:
inserting a first memory device to the memory system (pars. 27-28 the memory module that is to be replaced) and storing a first data value corresponding to the first memory device in a serial presence detect (SPD) device (pars. 28, the SPD device stores SPD Byte 5); ;
replacing the first memory device with a second memory device different from the first memory device (pars. 27-28 replacing the memory module);
in response to the replacement of the second memory device, changing the first data value into a second data value corresponding to the second memory device in the SPD device by an SPD writer (pars. 28, the SPD device updates SPD Byte 5 with the number of ranks for the memory module); and
in response to the first value being changed into the second data value the first data value is changed into the second data value, measuring, by a test pad, a first signal corresponding to the second memory device (pars. 29-30, the controller provides a chip-select signal to a memory, the BIOS code of the memory decoding (measuring) the chip-select signal received at the memory terminal (test pad). The memory controller is shown providing chip select signals to terminals of the memory in figures 1A and 5A).
Pauley fails to teach that the first signal is a bank signal, and verifying signal integrity.
Li teaches:
measuring, by a test pad, a first bank signal, thereby verifying signal integrity (pars. 85-86, “S209, performing a signal integrity test on the sixth batch of memory banks within the first frequency range to obtain a seventh batch of memory banks, wherein the seventh batch of memory banks are memory banks having no failure and/or failure in the signal integrity test; wherein the signal integrity test comprises a signal quality test at the time of interference. The signal integrity test belongs to the selectable test item of the memory bank detection, the memory bank after the signal integrity test has the cost higher than the universal memory bank, and the signal integrity test will be applied to the abnormal memory bank analysis and the new product memory bank introduction process. The signal integrity test mainly detects the quality of the signal when the signal passes through the link so as to avoid the signal quality not reaching the standard due to the interference and impedance in the link.”)
It would have been obvious to one of ordinary skill in the art, having the teachings of Pauly and Li before him before the earliest effective filing date, to modify the memory system of Pauley with the memory system of Li, in order to perform the signal integrity test, which verifies whether signal quality is below standard due to interference and impedance in the link, as taught by Li in par. 86.
With respect to claim 16, Pauley teaches a method for operating a memory system, comprising:
inserting a first memory device to the memory system (pars. 27-28 the memory module that is to be replaced) and storing a first data value corresponding to the first memory device in a serial presence detect (SPD) device (the SPD device stores SPD Byte 5);
replacing the first memory device with a second memory device different from the first memory device (pars. 27-28 replacing the memory module);
in response to the replacement of the second memory device, changing the first data value into a second data value corresponding to the second memory device (pars. 28, the SPD device updates SPD Byte 5 with the number of ranks for the memory module); and
in response to the first data value being changed into the second data value, measuring, by a test pad, a first signal (pars. 29-30, the controller provides a chip-select signal to a memory, the BIOS code of the memory decoding (measuring) the chip-select signal received at the memory terminal (test pad). The memory controller is shown providing chip select signals to terminals of the memory in figures 1A and 5A).
Pauley fails to teach that the first signal is a bank signal, and verifying signal integrity.
Li teaches:
measuring, by a test pad, a first bank signal, thereby verifying signal integrity (pars. 85-86, “S209, performing a signal integrity test on the sixth batch of memory banks within the first frequency range to obtain a seventh batch of memory banks, wherein the seventh batch of memory banks are memory banks having no failure and/or failure in the signal integrity test; wherein the signal integrity test comprises a signal quality test at the time of interference. The signal integrity test belongs to the selectable test item of the memory bank detection, the memory bank after the signal integrity test has the cost higher than the universal memory bank, and the signal integrity test will be applied to the abnormal memory bank analysis and the new product memory bank introduction process. The signal integrity test mainly detects the quality of the signal when the signal passes through the link so as to avoid the signal quality not reaching the standard due to the interference and impedance in the link.”)
It would have been obvious to one of ordinary skill in the art, having the teachings of Pauly and Li before him before the earliest effective filing date, to modify the memory system of Pauley with the memory system of Li, in order to perform the signal integrity test, which verifies whether signal quality is below standard due to interference and impedance in the link, as taught by Li in par. 86.
With respect to claim 17, Pauley and Li teach the limitations of the parent claim. Pauley further teaches the method of claim 16, further comprising:
storing a third data value corresponding to the first memory device in the SPD device (par. 28, total module capacity);
changing the third data value into a fourth data value corresponding to the second memory device by an SPD writer (par. 28, par. 28, after SPD Byte 5 is changed, total module capacity is calculated by multiplying the content of SPD Byte 5 by SPD Byte 31),
in response to the first data value and the third data value being changed into the second data value and the fourth data value, respectively, measuring, by the test pad, the first signal (pars. 29-30, the controller provides a chip-select signal to a memory, the BIOS code of the memory decoding (measuring) the chip-select signal received at the memory terminal (test pad). The memory controller is shown providing chip select signals to terminals of the memory in figures 1A and 5A).
Li teaches the first signal is a first bank signal (pars. 82-83)
Claim(s) 2 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pauley and Li as applied to claims 1 and 9 above, in view of Song et al., US PGPub 2021/0089395.
With respect to claim 2, Pauley and Li teach all of the limitations of the parent claim, but fails to teach wherein the first capacity is 8 gigabytes (GB), and the second capacity is 16 GB. Song further teaches the system of claim 1, wherein the first capacity is 8 gigabytes (GB), and the second capacity is 16 GB (par. 48).
It would have been obvious to one of ordinary skill in the art, having the teachings of Pauley, Li and Song before him before the earliest effective filing date, to modify the memory system of Pauley and Li with the memory system of Song, in order to increase DRAM density from 8gb to 16gb to avoid a degradation in performance, as taught by Song in par. 48.
With respect to claim 10, Pauley and Li teach all of the limitations of the parent claim, but fails to teach the first capacity is 8 gigabytes (GB), and the second capacity is 16 GB. Song further teaches the method of claim 9, wherein the first memory device has a first capacity of 8 gigabytes (GB), and the second memory device has a second capacity of 16 GB. (par. 48).
It would have been obvious to one of ordinary skill in the art, having the teachings of Pauley, Li and Song before him before the earliest effective filing date, to modify the memory system of Pauley and Li with the memory system of Song, in order to increase DRAM density from 8gb to 16gb to avoid a degradation in performance, as taught by Song in par. 48.
With respect to claim 11, Pauley, Li and Song teach all limitations of the parent claims. Pauley further teaches the method of claim 10, further comprising:
storing a third data value corresponding to the first memory device in the SPD device (par. 28, total module capacity);
changing the third data value into a fourth data value corresponding to the second memory device by the SPD writer (par. 28, par. 28, after SPD Byte 5 is changed, total module capacity is calculated by multiplying the content of SPD Byte 5 by SPD Byte 31),
in response to the first data value and the third data value being changed into the second data value and the fourth data value, respectively, measuring, by the test pad, the first signal (pars. 29-30, the controller provides a chip-select signal to a memory, the BIOS code of the memory decoding (measuring) the chip-select signal received at the memory terminal (test pad). The memory controller is shown providing chip select signals to terminals of the memory in figures 1A and 5A).
Li teaches the first signal is a first bank signal (pars. 82-83)
With respect to claim 12, Pauley, Li and Song teach all limitations of the parent claims. Pauley further teaches the method of claim 11, wherein the first data value is equal to “02”, and the second data value is equal to “04” (par. 28, Table 1, right column Hex has a value of “02” for 2 ranks and a value of “04” for 4 ranks).
Claim(s) 6 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pauley and Li as applied to claims 1, 3-6 and 16-17 above, in view of Tan et al., US PGPub 2024/0192755, hereafter, “Tan.”
With respect to claim 6, Pauley and Li teach all limitations of the parent claims, but fails to teach wherein the third data value is equal to “61”, and the fourth data value is equal to “62.” Tan further teaches the system of claim 5, wherein the third data value is equal to “61”, and the fourth data value is equal to “62” (pars. 57-59 and fig. 4, the byte range for SPD block 0 is 0 to 63, which includes “61” and 62”).
It would have been obvious, having the teachings of Pauley, Li and Tan before him before the earliest effective filing date, to modify the memory system of Pauley and Li with the memory system of Tan, in order to allow the BIOS to interpret DRAM DIMM type, maximum operating frequency, and write recovery time, as taught by Tan in par. 60.
With respect to claim 18, Pauley, Li and Tan teach the limitations of the parent claim. Pauley further teaches the method of claim 17, wherein the first data value is equal to “02”, the second data value is equal to “04” (par. 28, Table 1, right column Hex has a value of “02” for 2 ranks and a value of “04” for 4 ranks). Pauley fails to teach the third data value is equal to “61”, and the fourth data value is equal to “62”. Tan teaches the third data value is equal to “61”, and the fourth data value is equal to “62” (pars. 57-59 and fig. 4, the byte range for SPD block 0 is 0 to 63, which includes “61” and 62”).
It would have been obvious, having the teachings of Pauley, Li and Tan before him before the earliest effective filing date, to modify the memory system of Pauley and Li with the memory system of Tan, in order to allow the BIOS to interpret DRAM DIMM type, maximum operating frequency, and write recovery time, as taught by Tan in par. 60.
With respect to claim 19, Pauley, Li and Tan teach the limitations of the parent claim. Li further teaches the method of claim 17, further comprising: in response to the first data value being changed into the second data value, measuring, by the test pad, a second bank signal different from the first signal, and wherein during a period, the first bank signal is at a high voltage level, and the second bank signal is at the high voltage level (pars. 82-83).
With respect to claim 20, Pauley, Li and Tan teach the limitations of the parent claims. Pauley further teaches the method of claim 19, further comprising: in response to the first data value being changed into the second data value, measuring, by the test pad, a chip select signal, and wherein during the period, the chip select signal is at a low voltage level (pars. 29-30, where four chip select signals are used, the third chip select signal of four corresponding to the chip select signal).
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pauley, Li and Song as applied to claims 10-12 above, and further in view of Tan.
With respect to claim 13, Pauley, Li and Song teach all limitations of the parent claims, but fail to teach wherein the third data value is equal to “61”, and the fourth data value is equal to “62.” Tan further teaches the method of claim 12, wherein the third data value is equal to “61”, and the fourth data value is equal to “62” (pars. 57-59 and fig. 4, the byte range for SPD block 0 is 0 to 63, which includes “61” and 62”).
It would have been obvious, having the teachings of Pauley, Li, Song and Tan before him before the earliest effective filing date, to modify the memory system of Pauley, Li and Song with the memory system of Tan, in order to allow the BIOS to interpret DRAM DIMM type, maximum operating frequency, and write recovery time, as taught by Tan in par. 60
With respect to claim 14, Pauley, Li, Song and Tan teach the limitations of the parent claims. Li further teaches the method of claim 11, further comprising: in response to the first data value being changed into the second data value, measuring, by the test pad, a second bank signal different from the first signal, and wherein during a period, the first bank signal is at a high voltage level, and the second bank signal is at the high voltage level (pars. 82-83).
With respect to claim 15, Pauley, Li, Song and Tan teach the limitations of the parent claims. Pauley further teaches the method of claim 14, further comprising: in response to the first data value being changed into the second data value, measuring, by the test pad, a chip select signal, and wherein during the period, the chip select signal is at a low voltage level (pars. 29-30, where four chip select signals are used, the third chip select signal of four corresponding to the chip select signal).
Response to Arguments
Applicant's arguments filed 12/04/2025 have been fully considered but they are not persuasive. Firstly, the objection to the title is withdrawn due to the amendment. The rejections of claims 11-15 Under 35 USC 112 as being indefinite are withdrawn due to the claim amendment. Applicant’s arguments on pages 12-14 are directed towards Pauley failing to anticipate independent claims 1, 11 and 16, and Song also allegedly deficient in teaching the amended limitations. These arguments are moot, as the claims are now rejected under 35 USC 103, with the new Li reference supplied to teach a test pad configured to measure the first bank signal, and verifying signal integrity, which, in combination with Pauley, teaches “a test pad configured to measure the first bank signal, wherein in response to the first memory device being replaced by a second memory device having a second capacity different from the first capacity, the test pad measures the first bank signal, thereby verifying signal integrity,” as detailed in the rejection above. With respect to Applicant’s arguments on pages 14-15, regarding dependent claims 3, 7, 8, 14-15, and 19-20, the new Li reference has been supplied combine with Pauley to teach the features listed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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