DETAILED ACTION
Notice of Pre-AIA or AIA Status
This action is responsive to the amendment received on 08/27/2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The prior §112 rejections are withdrawn in view of the amended claims.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-4, 6-8, 10, 12-17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20230129825 A1), hereinafter referred to as Kim (newly cited).
Regarding claim 1: Kim teaches an electronic device (integrated circuit (IC) device) having at least two adjacent logic cells (see Figs. 1-2, two adjacent logic cells met by the repeating device regions RX1 and RX2, the claims do not preclude this treatment as a logic cell is not well defined), the at least two adjacent logic cells (RX1 and RX2) comprising:
at least one pair of vias (elements CAV, see Fig. 3B annotated below) disposed in an interlayer dielectric layer (interlayer insulating film 174), wherein a first via of the pair of vias is associated with a first logic cell (RX1) of the at least two adjacent logic cells and a second via of the pair of vias is associated with a second logic cell (RX2) of the at least two adjacent logic cells (See Fig. 3B annotated below); and
a spacer disposed between and separating the first via and the second via (etch stop film 172), wherein the spacer is formed of a first material (“the etch stop film 172 may include silicon carbide (SiC),
silicon nitride (SiN)”, para. [0058]) that differs from a second material (“the interlayer insulating film 174 may include a tetraethylorthosilicate (TEOS) film, a high-density plasma (HDP) film”, para. [0058]) that[AltContent: textbox ()] forms the interlayer dielectric layer, and wherein the first via abuts a first side of the spacer, and the second via abuts a second side of the spacer opposite the first side of the spacer. (See Fig. 3B annotated below).
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Fig. 3B from Kim (annotated): Dashed black line separates logic cells.
Regarding claim 3: Kim teaches the electronic device of claim 1, wherein: the spacer comprises silicon nitride. (“the etch stop film 172 may include silicon carbide (SiC), silicon nitride (SiN)”, para. [0058]).
Regarding claim 4: Kim teaches the electronic device of claim 1, wherein: the spacer surrounds a perimeter of the first logic cell. (The spacer layer 172 is deposited conformally over the entire device, see Figs. 25A and 25B, therefore the spacer surrounds each logic cell RX1 and RX2).
Regarding claim 6: Kim teaches the electronic device of claim 1, wherein: the second logic cell includes a peripheral edge opposite the first logic cell (See annotated Fig. 3B above, dashed black line) and the electronic device further comprises: a third logic cell adjacent the peripheral edge of the second logic cell at least one further pair of vias (Within each cell shown in Fig. 1 there are two are two device regions RX1 and RX2 as shown in Fig. 2, which are themselves considered logic cells, see Figure below, third and fourth vias, logic cells 1-4), wherein a third via of the further pair of vias is associated with the second logic cell and a fourth via of the further pair of back-to-back vias is associated with the third logic cell (See Figure annotated below); and a further spacer (See Figure below, black dashed boxes are considered to be the spacer and the further spacer) disposed between and separating the third via and the fourth via.
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Figure: Two of the cells shown in Fig. 2 of Kim are shown side-by-side, dashed outlines indicate regions of the etch stop film 172 considered to be the spacer and the further spacer. (As depicted in Figs. 1-2 the boundaries are periodic, combined with Figs. 3A and 3B the etch stop film 172 (spacer) abuts the vias in adjacent cells across rows both vertically (y direction) and horizontally (x direction).
Each device region RX1 and RX2 is itself considered a logic cell.
Regarding claim 7: Kim teaches the electronic device of claim 6, wherein: the further spacer comprises silicon nitride. (“the etch stop film 172 may include silicon carbide (SiC), silicon nitride (SiN)”, para. [0058]).
Regarding claim 8: Kim teaches the electronic device of claim 7, wherein: the further spacer surrounds a perimeter of the third logic cell. (See Figure above, black dashed box surrounding cell three is considered the further spacer)
Regarding claim 10: Kim teaches a semiconductor logic device (integrated circuit (IC) device) having at least two adjacent logic cells (see Figs. 1-2, two adjacent logic cells met by the repeating device regions RX1 and RX2, the claims do not preclude this treatment as a logic cell is not well defined), the at least two adjacent logic cells (RX1 and RX2) comprising:
at least one pair of vias (elements CAV, see Fig. 3B annotated above) disposed in an interlayer dielectric layer (interlayer insulating film 174), wherein a first via of the pair of vias is associated with a first logic cell of the at least two adjacent logic cells and a second via of the pair of vias is associated with a second logic cell of the at least two adjacent logic cells (See Fig. 3B annotated above); and
a spacer (etch stop film 172) disposed between and separating the first via and the second via, wherein the spacer is formed of a first material (“the etch stop film 172 may include silicon carbide (SiC), silicon nitride (SiN)”, para. [0058]) that differs from a second material (“the interlayer insulating film 174 may include a tetraethylorthosilicate (TEOS) film, a high-density plasma (HDP) film”, para. [0058]) that forms the interlayer dielectric layer, and wherein the first via abuts a first side of the spacer, and the second via abuts a second side of the spacer opposite the first side of the spacer. (See Fig. 3B annotated above).
Regarding claim 12: Kim teaches the semiconductor logic device of claim 10, wherein: the spacer comprises silicon nitride. (“the etch stop film 172 may include silicon carbide (SiC), silicon nitride (SiN)”, para. [0058]).
Regarding claim 13: Kim teaches the semiconductor logic device of claim 10, wherein: the spacer surrounds a perimeter of the first logic cell. (The spacer layer 172 is deposited conformally over the entire device, see Figs. 25A and 25B, therefore the spacer surrounds each logic cell).
Regarding claim 14: Kim teaches the semiconductor logic device of claim 10, wherein: the second logic cell includes a peripheral edge opposite the first logic cell (See Fig. 3B annotated above, black dashed line indicates cell boundary); the semiconductor logic device further comprising: a third logic cell adjacent the peripheral edge of the second logic cell (See Figure above); at least one further pair of vias, wherein a third via of the further pair of vias is associated with the second logic cell and a fourth via of the further pair of vias is associated with the third logic cell (See Figure above); And a further spacer disposed between and separating the third via and the fourth via (See Figure above, see rejection of claim 6).
Regarding claim 15: Kim teaches the semiconductor logic device of claim 14, wherein: the further spacer comprises silicon nitride. (“the etch stop film 172 may include silicon carbide (SiC), silicon nitride (SiN)”, para. [0058]).
Regarding claim 16: Kim teaches the semiconductor logic device of claim 15, wherein: the further spacer surrounds a perimeter of the third logic cell. (See Figure above, black dashed box surrounding cell three is considered the further spacer).
Regarding claim 17: Kim teaches, a method of forming a semiconductor logic device, comprising: forming at least two adjacent logic rows (See at least Fig. 2, Rx1 and RX2, a logic row can consist of single logic cells RX1 and RX2, RX1 and RX2 are considered to be logic rows); forming a spacer (See Figs. 3A and 3B, etch stop film 172 abuts vias CVA in both the x and y directions) about a peripheral edge of a first logic row of the at least two adjacent logic rows (Regions of the etch stop layer 172 that surround logic cell are considered spacers, see Figure above); and forming at least one pair of vias in adjacent logic cells of the at least two adjacent logic rows in an interlaver dielectric layer (See Fig. 3B annotated above, vias CAV are in insulating layer 174), wherein the spacer is formed of a first material (“the etch stop film 172 may include silicon carbide (SiC), silicon nitride (SiN)”, para. [0058]) that differs from a second material (“the interlayer insulating film 174 may include a tetraethylorthosilicate (TEOS) film, a high-density plasma (HDP) film”, para. [0058]) that forms the interlayer dielectric layer wherein the at least one pair of vias includes a first via and a second via, and wherein the first via abuts a first side of the spacer, and the second via abuts a second side of the spacer opposite the first side of the spacer. (See Fig. 3B annotated above).
Regarding claim 19: Kim teaches the method of claim 17, wherein: the spacer surrounds a perimeter of the first logic row. (The spacer layer 172 is deposited conformally over the entire device, see Figs. 25A and 25B, therefore the spacer surrounds each logic cell).
Regarding claim 20: Kim teaches the method of claim 19, further comprising: forming a third logic row (See Figure above, cell 3) adjacent to a second logic row (See Figure above, cell 2) of the at least two adjacent logic rows (See Figure above); forming a further spacer surrounding a perimeter of the third logic row (See Figure above); and forming at least one further pair of vias disposed in the interlayer dielectric layer, wherein a first via of the further pair of vias is associated with a logic cell of the second logic row and a second via of the further pair of vias is associated with a logic cell of the third logic row, and wherein the first via of the further pair of vias is separated from the second via of the further pair of vias by the further spacer. (See Figure above, see rejection of claim 6).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230129825 A1), hereinafter referred to as “Kim825” (newly cited) in view of Kim et al. (US 20220069129 A1) hereinafter referred to as “Kim129” (newly citied).
Regarding claim 5, Kim825 does not teach that the vias have an isotropic crystalline metal structure.
Kim129 teaches a method to form vias out of crystalline metal (“The fill metal 195 may include a crystalline metal.”, para. [0055]) and that such a structure improves the reliability of the semiconductor device and lower the contact resistance (See para. [0109]). (The examiner notes that a crystalline metal implies that there is an ordered isotropic structure.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate vias with an isotropic crystalline metal structure, as taught by Kim129, into the device taught by Kim825, in order to improve the device reliability and lower the contact resistance. The isotropic crystalline metal taught Kim129 is used in a similar device (with respect to the source/drain regions of a transistor) such that it could be substituted as the via material of Kim825 with a reasonable chance of success.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230129825 A1), hereinafter referred to as Kim (newly cited), in view of Xie et al. (US 20230207553 A1) hereinafter referred to as Xie (of record).
Regarding claim 9: Kim does not teach that the electronic device comprises at least one of: a music player; a video player; an entertainment unit ;a navigation device; a communications device ;a mobile device; a mobile phone; a smartphone; a personal digital assistant; a fixed location terminal; a tablet computer, a computer; a wearable device; a laptop computer; a server; an internet of things (IoT) device; or a device in an automotive vehicle.
Xie teaches an integrated circuit as disclosed herein can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the exemplary embodiments described herein (See para. [0136]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that a logic device you be used in a variety of electronic systems as disclosed by Xie. The logic devices of Xie and Kim are substantially similar, and their functions are well-known in the art. A person of ordinary skill in the art would have understood that logic devices are an integral part of many electronic systems, such as those listed in claim 9.
Response to Arguments
Arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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/ROBERT L STEWART/ Examiner, Art Unit 2898 /ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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