CTNF 18/610,898 CTNF 102233 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “back-to-back vias” in claims 1, 6, 10, 14, 17-18, and 20 has no commonly accepted meaning in the field. Furthermore, the specification does not provide a clear definition of the term, making the scope of the claims indefinite. For instance, “back-to-back vias” could mean that the first via associated with the first logic cell and the second via associated with the second logic cell are aligned in the same layer, or alternatively, that there is no via disposed between the first via and the second via. Claims 2-5, 7-9, 11-13, 15-16 and 19 are rejected since they inherit the indefiniteness of the claims from which they depend. For the purposes of examination, the term “back-to-back vias” will be interpreted to mean that there is no via disposed between the first via of the first logic cell and the second via of the second logic cell. The term “peripheral boundary” in claims 4, 8, 13, 16, and 19-20 is indefinite, and no clear definition for the term is provided in the specification. For instance, it could mean that the boundary must completely surround the logic cell on all sides, or alternatively, that the boundary forms a single edge between logic cells. For the purposes of examination, the term “peripheral boundary” will be interpreted to mean that the boundary forms at least a single edge between logic cells. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-2, 4, 6, 8-11, 13-15, and 16-20 are rejected under 35 U.S.C. 102( a)(1) and 102(a)(2 ) as being anticipated by Xie et al. (US 20230207553 A1) hereinafter referred to as Xie . Regarding claims 1 and 10, Xie discloses a semiconductor/electronic device having at least two adjacent logic cells (Fig. 9, elements C1, C2, C3; para. [0101]; C1 and C3 are adjacent and therefore back-to-back]), the at least two adjacent logic cells comprising: at least one pair of back-to-back vias, a first via (Fig. 9, elements 174; para. [0048]) associated with a first logic cell (Fig. 9, element C1; para. [0101]), and second via (Fig. 9, element 175; para. [0048]) associated with a second logic cell (Fig. 9, element C3; para. [0101]) a spacer disposed between and separating the first via and second via (Fig. 9, element 171 para. [0048]). Regarding claims 2 and 11, Xie further discloses that the first via abuts a first side of the spacer; and the second via abuts a second side of the spacer opposite the first side of the spacer (Fig. 9, elements 174, 175; para. [0048]; are in direct contact with the dielectric layer; Fig. 9, element 171). Regarding claims 4 and 13, Xie further discloses that the spacer forms a peripheral boundary about the first logic cell. (the dielectric layer makes up at least one edge of the cell boundary; Fig. 9, element 171). Regarding claims 6 and 14, Xie further discloses a second logic cell that includes a peripheral edge opposite the first logic cell (Fig 9., element C3 adjacent to C1) the electronic device further comprising: a third logic cell adjacent the peripheral edge of the second logic cell (Fig 9., element C2 adjacent to C3); at least one further pair of back-to-back vias (while not explicitly shown, para. [0101] explains the cells C1, C2, and C3 can be formed with lateral wiring in the MOL layer which extends across the cell boundaries), wherein a third via of the further pair of back-to-back vias is associated with the second logic cell and a fourth via of the further pair of back-to-back vias is associated with the third logic cell; and a further spacer (Fig. 9, element 171; each section of the dielectric layer is interpreted as a spacer) disposed between and separating the third via and the fourth via. Regarding claims 8 and 16, Xie further discloses the further spacer forms a peripheral boundary about the third logic cell (Fig. 9, element 171). Regarding claim 9, Xie further discloses the electronic device comprises at least one of: a music player; a video player; an entertainment unit; a navigation device; a communications device; a mobile device; a mobile phone; a smartphone; a personal digital assistant; a fixed location terminal; a tablet computer, a computer; a wearable device; a laptop computer; a server; an internet of things (IoT) device; or a device in an automotive vehicle (para. [0136]). Regarding claim 17, claim 17 is rejected in the same manner as claim 1 (the term logic row is interpreted by the examiner to mean a row containing a least one logic cell). Regarding claim 18, claim 18 is rejected in the same manner as claim 2. Regarding claim 19, claim 19 is rejected in the same manner as claim 4 (the term logic row is interpreted by the examiner to mean a row containing a least one logic cell). Regarding claim 20, claim 20 is rejected in the same manner as claim 6 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3, 7, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Choi et al. (US 20240339536 A1) hereinafter referred to as “Choi” . Regarding claims 3, 7, 12, and 15, Xie teaches silicon nitride as a common insulating/dielectric material used in semiconductor manufacturing (para. [0081]), Xie also teaches that the implementation of the isolation structure disposed in the cell boundary region between the first and second cells allows for reduction in the cell-to-cell spacing between the first and second cells (para. [0010]). However, Xie does not explicitly teach that the spacer (dielectric layer; Fig. 9, element 171) is comprised of silicon nitride. Choi teaches that silicon nitride can be disposed along a boundary of a standard cell as a cell isolation structure (paras. [0142] and [0143]; Fig. 7, element 120CT). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use silicon nitride as a material defining a cell boundary, as this is simply combining prior art elements according to known methods to yield predictable results . 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Rastogi et al. (US 20180157781 A1) hereinafter referred to as “Rastogi” . Regarding claim 5, Xie does not explicitly teach that the vias have an isotropic crystalline metal structure. As best understood, isotropic crystalline metal structures are achieved when using a damascene manufacturing process. Rastogi teaches that vias may be formed by a damascene process (para. [0084]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate vias with an isotropic crystalline metal structure, as this is simply combining prior art elements according to known methods to yield predictable results. Citation of Pertinent Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Baek et al. (US 20210328056 A1), and You et al. (US 20210134837 A1) are cited to teach standard cells with adjacent vias and insulating boundaries between cells . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)270-0853. The examiner can normally be reached M-F 9:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERT L STEWART/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898 Application/Control Number: 18/610,898 Page 2 Art Unit: 2898 Application/Control Number: 18/610,898 Page 3 Art Unit: 2898 Application/Control Number: 18/610,898 Page 4 Art Unit: 2898 Application/Control Number: 18/610,898 Page 5 Art Unit: 2898 Application/Control Number: 18/610,898 Page 6 Art Unit: 2898 Application/Control Number: 18/610,898 Page 7 Art Unit: 2898
Prosecution Insights