DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (EP 2 333 946 B1).
Regarding claim 1, in Figure 4, Lee discloses a power supply circuit, comprising a processing circuit (410), a load circuit (130, 135) and a feedback circuit (420, 430) which are sequentially connected (Figure 4), wherein the feedback circuit is connected to an output terminal of the load circuit and the processing circuit (Figure 4), and is configured to obtain a voltage of the output terminal of the load circuit and generate a sampling value (page 5, 4th and 5th paragraphs), the processing circuit is configured to control a voltage of the output terminal of the load circuit according to the sampling value generated by the feedback circuit (page 5, 2nd paragraph); and wherein the power supply circuit further comprises: a differential circuit (415), connected to the load circuit and the feedback circuit by using a differential trace (Figure 4).
Regarding claim 2, Lee discloses wherein the feedback circuit comprises: a first resistor, wherein a first terminal of the first resistor is connected to a first node and a second terminal of the first resistor is connected to a third node; a second resistor, wherein a first terminal of the second resistor is connected a second node and a second terminal of the second resistor is connected to the third node; a first capacitor, wherein a first terminal of the first capacitor is connected to the first node and a second terminal of the first capacitor is connected to a fourth node; and a second capacitor, wherein a first terminal of the second capacitor is connected to a fifth node and the second terminal of the second capacitor is connected to a sixth node, wherein the first node is connected to the output terminal of the load circuit, the second node is connected to a ground terminal of the load circuit, the fifth node is connected to an input terminal of the processing circuit and the sixth node is connected to a ground terminal of the processing circuit (Figure 4).
Regarding claim 3, Lee discloses wherein the differential circuit comprises: a third resistor, wherein a first terminal of the third resistor is connected to the first node and a second terminal of the third resistor is connected to a seventh node; a fourth resistor, wherein a first terminal of the fourth resistor is connected to the second node and a second terminal of the fourth resistor is connected to an eighth node; and a third capacitor, wherein a first terminal of the third capacitor is connected to the seventh node and a second terminal of the third capacitor is connected to the eighth node, wherein the seventh node is connected to the output terminal of the load circuit, and the eighth node is connected to the ground terminal of the load circuit (Figure 4).
Regarding claim 4, Lee discloses wherein the differential trace comprises: a first differential wire, one terminal of the first differential wire is connected to the output terminal of the load circuit, and the other terminal of the first differential wire is connected to an input terminal of the feedback circuit; and a second differential wire, one terminal of the second differential wire is connected to an input terminal of the load circuit, and the other terminal of the second differential wire is connected to the input terminal of the feedback circuit, wherein a distance between the first differential wire and the second differential wire is equal (Figure 4).
Regarding claim 5, Lee discloses wherein a polarity of the first differential wire is opposite to a polarity of the second differential wire (Figure 4).
Regarding claim 6, Lee discloses wherein the power supply circuit further comprises a power supply output circuit and a power supply filtering circuit, the power supply output circuit is connected between the processing circuit and the power supply filtering circuit, and the power supply filtering circuit is connected between the processing circuit and the load circuit; wherein the power supply output circuit is configured to generate a power output voltage from a voltage output by the processing circuit, and the power supply filtering circuit is configured to filter the power output voltage (Figure 4).
Regarding claim 7, Lee discloses wherein the power supply circuit further comprises a power supply input circuit, the power supply input circuit is connected to an input terminal of the processing circuit, and the processing circuit comprises: a switch transistor, wherein a terminal of the switch transistor is connected to the power supply input circuit, another terminal of the switch transistor is connected to the load circuit, and a load terminal of the switch transistor is connected to an output terminal of a control unit; and the control unit, wherein an input terminal of the control unit is connected to the feedback circuit, and the control unit is configured to control a voltage of the output terminal of the load circuit according to the sampling value generated by the feedback circuit (Figure 4).
Regarding claim 8, Lee discloses wherein the switch transistor is a Metal-Oxide-Semiconductor (MOS) transistor (Figure 4).
Regarding claim 9, in Figure 4, Lee discloses a PCB circuit board, comprising a power supply circuit; wherein the power supply circuit comprises a processing circuit (410), a load circuit (130, 135) and a feedback circuit (420, 430) which are sequentially connected (Figure 4), wherein the feedback circuit is connected to an output terminal of the load circuit and the processing circuit (Figure 4), and is configured to obtain a voltage of the output terminal of the load circuit and generate a sampling value (page 5, 4th and 5th paragraphs), the processing circuit is configured to control a voltage of the output terminal of the load circuit according to the sampling value generated by the feedback circuit (page 5, 2nd paragraph); and wherein the power supply circuit further comprises a differential circuit (415), connected to the load circuit and the feedback circuit by using a differential trace (Figure 4).
Regarding claim 10, in Figure 4, Lee discloses a power supply device, comprising a PCB circuit board; wherein the PCB circuit board comprises a power supply circuit; wherein the power supply circuit comprises a processing circuit (410), a load circuit (130, 135) and a feedback circuit (420, 430) which are sequentially connected (Figure 4), wherein the feedback circuit is connected to an output terminal of the load circuit and the processing circuit (Figure 4), and is configured to obtain a voltage of the output terminal of the load circuit and generate a sampling value (page 5, 4th and 5th paragraphs), the processing circuit is configured to control a voltage of the output terminal of the load circuit according to the sampling value generated by the feedback circuit (page 5, 2nd paragraph); and wherein the power supply circuit further comprises a differential circuit (415), connected to the load circuit and the feedback circuit by using a differential trace (Figure 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847