DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/20/2024 and 12/3/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 2 is objected to because of the following informalities: The recitation “is fabricated in using Group” should be corrected to “is fabricated using Group”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 14 and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the US Patent US 11,698,404 by Lin et al., (Lin hereafter).
Regarding claim 1, Lin teaches in Figure 4, a dynamic on-resistance and threshold voltage instability evaluation circuit for power devices, comprising:
a half-bridge circuit (21+9), being electrically connected to and receiving an input voltage (VDD), wherein the half-bridge circuit comprises a first switch element (21) and a device under test (9) which are connected in series (when transistor 22 is “off”);
an assemble load (5) being electrically connected between the input voltage and a midpoint of the half-bridge circuit, and the assemble load enabling repetitive hard-switching operation of the device under test for dynamic on-resistance measurement of the device under test (see col. 6, lines 3-7); and
a switch combining circuit (22+3), being electrically connected between the half-bridge circuit and a ground terminal (Gnd), and the switch combining circuit enabling threshold voltage measurement of the device under test (see col. 6, lines 3-7).
As to claim 2, Lin teaches in Figure 4, the dynamic on-resistance and threshold voltage instability evaluation circuit for power devices according to claim 1, wherein the device under test is a power device (transistor 9), and the power device is fabricated in using Group III-N based semiconductor materials (AlGaN/GaN transistor, see col. 3, lines 23 – See also, the application’s Specification, page 5, line 12).
As to claim 3, Lin teaches in Figure 4, the dynamic on-resistance and threshold voltage instability evaluation circuit for power devices according to claim 1, wherein the first switch element (21) is a metal oxide semiconductor field effect transistor (MOSFET) (see col.. 7, line 57), a drain terminal (211) of the metal oxide semiconductor field effect transistor (21) is electrically connected to the input voltage (Vdd, through resistor 6),
a gate terminal (213) of the metal oxide semiconductor field effect transistor is electrically connected with a first gate driver (not shown, providing signal “CTRL1”) for receiving a first driving voltage such that the first driving voltage is a gate driving voltage of the first switch element, and
a source terminal (212) of the metal oxide semiconductor field effect transistor is electrically connected with the assemble load (5) and the device under test (9).
As to claim 4, Lin teaches in Figure 4, the dynamic on-resistance and threshold voltage instability evaluation circuit for power devices according to claim 3, wherein the device under test (9) is a Group III-N based MOSFET (AlGaN/GaN MOSFET transistor, see col. 3, lines 21-25), a drain terminal (91) of the Group III-N based MOSFET is electrically connected to the source terminal (212) of the first switch element (21) and the assemble load (5), a gate terminal (93) of the Group III-N based MOSFET is electrically connected with a second gate driver (not shown driver providing signal “TEST”) for receiving a second driving voltage such that the second driving voltage is a gate driving voltage of the device under test, and a source terminal (92) of the Group III-N based MOSFET is electrically connected with the switch combining circuit (22+3).
Regarding claim 14, Lin teaches in Figure 4, an operation method of a dynamic on-resistance and threshold voltage instability evaluation circuit for power devices, comprising:
providing a half-bridge circuit (21+9) and electrically connecting the half-bridge circuit to an input voltage (Vdd or 8), the half-bridge circuit comprising a first switch element (21) and a device under test (9) which are connected in series (when transistor 22 is “off”);
electrically connecting an assemble load (5) between the input voltage and a midpoint of the half-bridge circuit for enabling repetitive hard-switching operation of the device under test for dynamic on-resistance measurement of the device under test (see col. 6, lines 3-7); and
electrically connecting a switch combining circuit (22+3) between the half-bridge circuit and a ground terminal (Gnd), such that the switch combining circuit enables threshold voltage measurement of the device under test (see col. 6, lines 3-7).
As to claim 23, Lin teaches the operation method of the dynamic on-resistance and threshold voltage instability evaluation circuit for power devices according to claim 14, wherein the device under test is a power device (transistor 9), and the power device is fabricated in using Group III-N based semiconductor materials (AlGaN/GaN MOSFET transistor, see col. 3, lines 21-25).
Allowable Subject Matter
Claims 5-13 and 15-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art of record doesn’t teach alone or in combination, the dynamic on-resistance and threshold voltage instability evaluation circuit, wherein the assemble load comprises a resistor and an inductor which are connected in series, one end of the resistor is electrically connected with the input voltage while another end of the resistor is electrically connected with the inductor, and the inductor is further electrically connected to a joint where the first switch element and the device under test are connected, in combination with all other elements recited.
Regarding claim 6, the prior art of record doesn’t teach alone or in combination, the dynamic on-resistance and threshold voltage instability evaluation circuit, wherein the switch combining circuit comprises a second switch element and a capacitor which are connected in parallel, the second switch element is a metal oxide semiconductor field effect transistor (MOSFET), and wherein a drain terminal of the metal oxide semiconductor field effect transistor is electrically connected to the device under test of the half-bridge circuit, a gate terminal of the metal oxide semiconductor field effect transistor is electrically connected with a third gate driver for receiving a third driving voltage such that the third driving voltage is a gate driving voltage of the second switch element, and a source terminal of the metal oxide semiconductor field effect transistor is electrically connected with the ground terminal, in combination with all other elements recited.
As to claims 7-13, the claims are also objected as they further limit objected claim 6 above.
Regarding claim 15, the prior art of record doesn’t teach alone or in combination, the operation method of the dynamic on-resistance and threshold voltage instability evaluation circuit, wherein the switch combining circuit comprises a second switch element and a capacitor which are connected in parallel, the second switch element is a metal oxide semiconductor field effect transistor, and wherein a drain terminal of the metal oxide semiconductor field effect transistor is electrically connected to the device under test of the half-bridge circuit, a gate terminal of the metal oxide semiconductor field effect transistor is electrically connected with a gate driver for receiving a gate driving voltage, and a source terminal of the metal oxide semiconductor field effect transistor is electrically connected with the ground terminal, in combination with all other elements recited.
As to claims 16-22, the claims are objected as they further limit objected claim 15 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- The US Patent US 9,984,190 by Aurich et al., directed to systems for determining parameters of a power MOSFET.
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/RICHARD ISLA/ Primary Patent Examiner, Art Unit 2858 March 10, 2026
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