DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-13 & 19-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 & 16-20 of copending Application No. 19/292,281 (reference application), in view of Chen et al. (US 2019/0140637 A1), hereinafter Chen. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
18/611,042
19/292,281
Claim 1.
A driving circuit, comprising: a driving stage, comprising a first driving device and a second driving device configured to drive a power device; and a first subcircuit, electrically connected to the driving stage, the first subcircuit comprising: a first precharge circuit; and a first predriving circuit, electrically connected to the first precharge circuit and the first driving device, wherein the first precharge circuit is configured to: in response to an input signal of the driving circuit having a first signal level, generate a first precharging voltage, and in response to the input signal having a second signal level different from the first signal level, fully turn on, based on the first precharging voltage, a first predriving device in the first predriving circuit to drive the first driving device.
Claim 1.
A driving circuit, comprising: a first driving device configured to drive a power device; a first precharge circuit; and a first predriving circuit electrically connected to the first precharge circuit and the first driving device, wherein the first precharge circuit is configured to: in response to an input signal of the driving circuit having a first signal level, generate a first precharging voltage, and in response to the input signal having a second signal level different from the first signal level, fully turn on, based on the first precharging voltage, a first device in the first precharge circuit to supply a first boost voltage to the first predriving circuit to drive the first driving device.
Claim 2.
The driving circuit of claim 1, further comprising: a second driving device configured to drive the power device; a second precharge circuit; and a second predriving circuit electrically connected to the second precharge circuit and the second driving device, wherein the second precharge circuit is configured to: in response to the input signal having the second signal level, generate a second precharging voltage, and in response to the input signal having the first signal level, fully turn on, based on the second precharging voltage, a second device in the second precharge circuit to supply a second boost voltage to a second predriving device in the second predriving circuit to drive the second driving device.
Claim 19.
A method of operating a driving circuit, wherein the driving circuit comprises a first precharge circuit, a first predriving circuit, and a driving stage, the method comprising: in response to an input signal being in a first logic state: storing, by a first capacitor in the first precharge circuit, a first precharging voltage; and in response to the input signal being in a second logic state different from the first logic state: boosting, by the first precharge circuit using the stored first precharging voltage, a first driving voltage for the first predriving circuit, and driving, by the first predriving circuit with the boosted first driving voltage, a first driving device in the driving stage to provide a first voltage corresponding to a power supply voltage to a power device.
Claim 16.
A method of operating a driving circuit to drive a power device, the method comprising: in response to an input signal being in a first logic state: storing a first precharging voltage; and in response to the input signal being in a second logic state different from the first logic state: boosting, using the stored first precharging voltage, a first driving voltage, and driving, with the boosted first driving voltage, a first driving device in the driving circuit to provide a first voltage corresponding to a first power supply voltage to drive the power device, wherein the driving circuit is in a first power domain of the first power supply voltage, and the power device is in a second power domain of a second power supply voltage greater than the first power supply voltage.
The reference application does not disclose a first capacitor in the first precharge circuit to store the precharging voltage.
However, Chen discloses, in figure 2, a first capacitor in the first precharge circuit (capacitor 120 fed by diode 118) to store the precharging voltage (Para [0037], “in this state, the bootstrap capacitor is charged by the supply voltage V.sub.DD through the bootstrap diode 118”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the capacitor of Chen to store the precharge voltage of the reference application, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions [i.e., utilizing a capacitor to store a charge], and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 14 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Rooij et al. (US 10,243,546 B2), hereinafter Rooij.
Regarding claim 14, Rooij discloses, in figure 2 & 9, Multi-stage precharging circuitry for a driving circuit (Q.sub.1 to Q.sub.8 driving Q.sub.9 and Q.sub.10), the multi-stage precharging circuitry comprising:
a first precharge circuit (Q.sub.4, Q.sub.5, and capacitor C1), configured to generate a first boost driving voltage higher than a power supply voltage supplied to the multi-stage precharging circuitry (Col. 3, Lines 54-57, “The first stage works as a bootstrap supply where the voltage across capacitor 20 (C1=5 pF) level shifts the inverted input signal from between 0 V and 5 V to between 5 V and 10 V”), in response to an input signal having a first signal level (Col. 3, Lines 39-41, “the level shifter to increase the voltage magnitude of the input (A.sub.in) by a factor of two for the logic high only”);
a second precharge circuit (Q.sub.6, Q.sub.7, Q.sub.8, capacitor C2, and capacitor C5), electrically connected to the first precharge circuit (electrically connected to Q.sub.5 at the node formed at the intersection to capacitor C2), to generate a second boost driving voltage based on the first boost driving voltage (Col. 3, Lines 50-52, “The second stage works in the same manner as the logic inverter except its supply voltage is 10 V”…second stage of the level shifter generates a second boost driving voltage based on the first stage generated boost driving voltage of between 5V and 10V), in response to the input signal having the first signal level (at the logic high level, the first generated boost driving voltage is applied to the second stage of the level shifter to generate the second boost driving voltage).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 & 4 are rejected under 35 U.S.C. 103 as being unpatentable over Rooij in view of Chen.
Regarding claim 1, Rooij discloses, in figure 9, A driving circuit, comprising:
a driving stage (26 & 28), comprising a first driving device and a second driving device configured to drive a power device (transistors 26 & 28 drive a power device Q.sub.100); and
a first subcircuit (elements before 26 & 28 of Figure 9), electrically connected to the driving stage (elements connected to the gates of 26 & 28), the first subcircuit comprising:
a first precharge circuit (Q.sub.4, Q.sub.5, and capacitor C1); and
wherein the first precharge circuit (Q.sub.4, Q.sub.5, and capacitor C1) is configured to:
in response to an input signal of the driving circuit having a first signal level (Col. 3, Lines 39-41, “the level shifter to increase the voltage magnitude of the input (A.sub.in) by a factor of two for the logic high only”), generate a first precharging voltage (Col. 3, Lines 54-57, “The first stage works as a bootstrap supply where the voltage across capacitor 20 (C1=5 pF) level shifts the inverted input signal from between 0 V and 5 V to between 5 V and 10 V”), but fails to disclose a first predriving circuit, electrically connected to the first precharge circuit and the first driving device; and
in response to the input signal having a second signal level different from the first signal level, fully turn on, based on the first precharging voltage, a first predriving device in the first predriving circuit to drive the first driving device.
However, Chen discloses, in figure 5, a first predriving circuit (215 & 216), electrically connected to the first precharge circuit and the first driving device (215 and 216 are electrically connected to 211, 212, 214, 218, & 220, see figure 5); and
wherein the first precharge circuit (211, 212, 214, 218, & 220) is configured to: in response to the input signal (Vi) having a second signal level different from the first signal level (logic low state), fully turn on, based on the first precharging voltage, a first predriving device in the first predriving circuit to drive the first driving device (Para [0043], “the capacitor 220 is charged when the pull-down transistor 215 is turned on…The capacitance value needs to store sufficient charge to turn on the pull-up transistor 216 when the V.sub.i input terminal is at the logic low state and the pull-down transistor 215 is turned off”…i.e., based on the first precharging voltage stored in capacitor 220, first predriving device 216 is fully turned on to drive power device 208).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the predrive operation voltage of Chen in the precharge circuit of Rooij, to achieve the benefit of employing a self-bootstrap scheme that allows the supply voltage of the gate voltage to achieve rail-to-rail output, enhanced driving capability and fast charging speed (Chen, Para [0029]).
Regarding claim 4, Rooij in view of Chen disclose the driving circuit of claim 1, and Rooij continus to disclose, in figure 9, wherein the first driving device and the second driving device comprise GaN-based enhancement-mode high-electron-mobility transistors (E-HEMT) (Col. 1 & 4, Lines 18-20 & 5-6, “GaN transistors…GaN offers…high electron mobility…GaN FET 28…GaN FET 26”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Rooij in view of Chen as applied to claims 1 & 4 above, and further in view of Lai et al. (US 2022/0131456 A1), hereinafter Lai.
Regarding claim 5, Rooij in view of Chen disclose the driving circuit of claim 1, but fail to disclose wherein the first driving device and the second driving device comprise silicon-based enhancement-mode N-type transistors.
However, Lai discloses, in figure 1, wherein the first driving device (SW4) and the second driving device (SW3) comprise silicon-based enhancement-mode N-type transistors (Para [0030], “switching element of FIG. 1 may be…silicon carbide based”…depicted as an enhancement mode N-type MOSFET).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the silicon-based transistors of Lai as the driving devices of Rooij and Chen, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions [i.e., utilizing well known transistor types for differing functions], and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Rooij in view of Roberts et al. (US 9,525,413 B2), hereinafter Roberts.
Regarding claim 15, Rooij discloses the multi-stage precharging circuitry of claim 14, but fails to disclose a first predriving circuit, electrically connected to the second precharge circuit and configured to drive a first driving device of the driving circuit, wherein the first predriving circuit comprises a first predriving device configured to be fully turned on by the second boost driving voltage, in response to the input signal having the first signal level.
However, Roberts discloses, in figure 10, a first predriving circuit (transistors D1 & D2), electrically connected to the second precharge circuit (voltage doubler of 440) and configured to drive a first driving device of the driving circuit (Col. 10, Lines 16-17, “voltage doubler to provide the required higher gate drive voltage Vcc.sub.1 for D1”…to drive D3), wherein the first predriving circuit comprises a first predriving device configured to be fully turned on by the second boost driving voltage (Col. 10, Lines 36-38, “the voltage doubler develops a suitable boost voltage Vcc.sub.1 at 12V to turn on D1 fully.”), in response to the input signal having the first signal level (Col. 10, Lines 24-26, “ When Vin is high…provide gate current to D1”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the operation of Roberts in the multi-stage precharging circuitry of Rooij, to achieve the benefit of providing a required higher gate drive voltage to a GaN transistor that allows the power device to transition without shoot-through current and without the need for an additional driver to the gate of the power device (Roberts, Col. 10, Lines 16-21).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Rooij in view of Chen, and further in view of Yang (US 2018/0191342 A1).
Regarding claim 19, A method of operating a driving circuit, wherein the driving circuit comprises a first precharge circuit (Q.sub.4, Q.sub.5, and capacitor C1) and a driving stage (transistors 26 & 28 drive a power device Q.sub.100), the method comprising:
in response to an input signal being in a first logic state (Col. 3, Lines 39-41, “the level shifter to increase the voltage magnitude of the input (A.sub.in) by a factor of two for the logic high only”):
storing, by a first capacitor in the first precharge circuit (capacitor C1), a first precharging voltage (Col. 3, Lines 54-57, “The first stage works as a bootstrap supply where the voltage across capacitor 20 (C1=5 pF) level shifts the inverted input signal from between 0 V and 5 V to between 5 V and 10 V”); but fails to disclose a first predriving circuit and in response to the input signal being in a second logic state different from the first logic state:
boosting, by the first precharge circuit using the stored first precharging voltage, a first driving voltage for the first predriving circuit, and
driving, by the first predriving circuit with the boosted first driving voltage, a first driving device in the driving stage to provide a first voltage corresponding to a power supply voltage to a power device.
However, Chen discloses, in figure 5, a first predriving circuit (215 & 216) and in response to the input signal (Vi) being in a second logic state different from the first logic state (logic low state):
boosting, by the first precharge circuit using the stored first precharging voltage, a first driving voltage for the first predriving circuit (Para [0043], “the capacitor 220 is charged when the pull-down transistor 215 is turned on…The capacitance value needs to store sufficient charge to turn on the pull-up transistor 216 when the V.sub.i input terminal is at the logic low state and the pull-down transistor 215 is turned off”…i.e., based on the first precharging voltage stored in capacitor 220, first predriving device 216 is fully turned on via a boosted driving voltage from 213 & 214 to drive power device 208).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the predrive operation voltage of Chen in the precharge circuit of Rooij, to achieve the benefit of employing a self-bootstrap scheme that allows the supply voltage of the gate voltage to achieve rail-to-rail output, enhanced driving capability and fast charging speed (Chen, Para [0029]).
In combination, Rooij and Chen fail to disclose in response to the input signal being in a second logic state different from the first logic state:
driving, by the first predriving circuit with the boosted first driving voltage, a first driving device in the driving stage to provide a first voltage corresponding to a power supply voltage to a power device.
However, Yang discloses, in figure 3, in response to the input signal being in a second logic state different from the first logic state (Para [0056], “when the control signal SC is at the low voltage level”):
driving, by the first predriving circuit with the boosted first driving voltage (Para [0058], “the high-side voltage VH, which is equal to the sum of the voltage of the first node N1 and the voltage across the first capacitor C1, is boosted”), a first driving device in the driving stage to provide a first voltage corresponding to a power supply voltage to a power device (Para [0057], ”to boost the high-side voltage VH through the first capacitor C1 for fully turning ON the high-side transistor 221”…to supply a voltage to power transistor 210).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the operation of Yang in the driving circuit of Rooij and Chen, to achieve the benefit of generating a high-side voltage that exceeds the supply voltage, such that the gate-to-source voltage of the high-side transistor at least exceeds the threshold voltage to apply the supply voltage to the power device (Yang, Para [0049]).
Allowable Subject Matter
Claims 2-3, 6-13, 16-18 & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Castaldo et al. (US 2013/0335121 A1) [Figure 3. Discloses an electronic switch may include transfer transistor having a first conduction terminal for receiving an input signal, a second conduction terminal, and a control terminal. The transfer transistor may enable/disable a transfer of the input signal from the first conduction terminal to the second conduction terminal according to a control signal. The control signal may take a first value and a second value different from the first value, a difference between the first value and the second value defining, in absolute value, an operative value of the control signal. The electronic switch may further comprise a driving circuit for receiving the input signal and the control signal, and for providing a driving signal equal to the sum between the input signal and the operative value of the control signal to the control terminal of the transfer transistor.]
Wang et al. (US 2011/0025397 A1) [Figure 4. Discloses A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
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/TYLER J PERENY/ Examiner, Art Unit 2836
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