DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 8/5/2026 "Reply" elects with traverse Invention I and identifies as reading on claims 1-12.
Applicant contends that the search and examination of all the claims can be made without serious burden. In the restriction requirement Examiner has set forth why the restriction requirement is proper and that there would be a serious search and/or examination burden if the restriction were not required at least because the inventions have acquired a separate status in the art due to their recognized divergent subject matter and require a different field of search. Accordingly, the restriction requirement is maintained and Examiner has withdrawn claims 13-20 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon (US Pub. No. 2018/0350905).
Regarding claim 1, in FIG. 11P, Yoon discloses an integrated circuit device, comprising: a substrate (110, paragraph [0071]) including a cell array area (CELL) and a peripheral circuit area (CORE/PERI) next to the cell array area; an isolation layer defining an activation region of the substrate in the peripheral circuit area, the isolation layer including a first insulation pattern (112B) and a second insulation pattern (112C), the second insulation pattern surrounding the first insulation pattern; and a gate structure (PGS) on the substrate in the peripheral circuit area, wherein the second insulation pattern includes one or more surfaces defining a recess into an upper surface of the substrate in a vertical direction, the vertical direction extending perpendicular to the upper surface of the substrate.
Regarding claim 2, in FIG. 11P, Yoon discloses a protective layer (166) covering the gate structure and an upper surface of the isolation layer, wherein the protective layer includes a first protrusion filling the recess of the second insulation pattern and is rounded downward in the vertical direction.
Regarding claim 4, in FIG. 11P, Yoon discloses that the second insulation pattern includes a material (TOSZ, paragraph 0074) having etch selectivity with respect to the first insulation pattern (SiN, paragraph 0074).
Regarding claim 5, in FIG. 11P, Yoon discloses that a vertical level of an upper surface of the first insulation pattern is a first level, a vertical level of a bottom surface of the recess is a second level, and the second level is lower than the first level.
Regarding claim 11, in FIG. 11P, Yoon discloses an insulating spacer (outermost layer of 162, paragraph [0117]) on a side surface of the gate structure, wherein the gate structure includes a peripheral circuit gate electrode (150) and a gate capping pattern (152) on the peripheral circuit gate electrode, and a vertical level of an upper surface of the insulating spacer and a vertical level of an upper surface of the gate capping pattern are different from each other.
Regarding claim 12, in FIG. 11P, Yoon discloses the insulating spacer is spaced apart in a horizontal direction from the gate structure (by the inner layers of 162) and the upper surface of the substrate, the horizontal direction extending parallel to the upper surface of the substrate.
Allowable Subject Matter
Claims 3 and 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, in FIG. 11P, Yoon discloses an interlayer insulating layer (190, paragraph [0128]) at least partially covering the protective layer.
However, the prior art failed to disclose or reasonably suggest the claimed integrated circuit device particularly characterized by the interlayer insulating layer including a second protrusion protruding in the vertical direction from a portion vertically overlapping the recess, and the second protrusion is rounded downward in the vertical direction.
Regarding claim 6, in FIG. 11P, Yoon discloses a bit line (BL, paragraph [0120]) on the substrate and an insulating capping structure on the bit line in the cell array area, wherein the bit line and the insulating capping structure extend in a first horizontal direction parallel to the upper surface of the substrate, the insulating capping structure includes a lower capping pattern (156, paragraph [0111]).
However, the prior art failed to disclose or reasonably suggest the claimed integrated circuit device particularly characterized by an upper capping pattern on the lower capping pattern, and a first insulating layer pattern between the lower capping pattern and the upper capping pattern, and the first insulating layer pattern and the upper capping pattern each have a chamfered shape wherein respective opposite sides of each of the first insulating layer pattern and the upper capping pattern are recessed to be round in a second horizontal direction crossing the first horizontal direction and parallel to the upper surface of the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
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