DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species X (claims 1-15) in the reply filed on 7/30/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: in Fig. 5D, reference character 150’. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-10, and 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kadoguchi et al (US 2022/0392834 and Kadoguchi hereinafter).
As to claims 1-3, 6-10, and 12-15: Kadoguchi discloses [claim 1] a power module (Figs. 18 and 22; [0107]) comprising: a first substrate (Fig. 18; 30; [0054]), the first substrate (30) comprising a plurality of layers (34, 32, 38; [0054]) that are stacked in a first direction (vertical direction) and extend in a second direction (horizontal direction) crossing the first direction (vertical direction); a semiconductor chip (Fig. 18; 12; [0048] and [0049]) connected to the first substrate (30) in the first direction (vertical direction); and a first lead (Fig. 18; 14; [0048]) that extends in the first direction (14 is three-dimensional and extends in all 3 orthogonal directions, including the first/vertical direction), the first lead (14) having (i) a first end (adjacent 10 30) that is electrically connected (through 144; [0115]) to the first substrate (30) and (ii) a second end (outside of 11; [0047]) that is exposed to an outside (outside of 11) of the power module; [claim 2] wherein the second end (Fig. 18; outside of 11) of the first lead (14) is connected to an external terminal (positive electrode of external power supply; [0108]) disposed outside of the power module; [claim 3] further comprising: a molding (Fig. 18; 11; [0047]) that covers at least a part of each of the first substrate (30), the semiconductor chip (12), and the first lead (14), wherein the second end (outside of 11) of the first lead (14) defines an exposed surface (portion of 14 outside of 11 is exposed) that is exposed outside of the molding (11); [claim 6] wherein the plurality of layers (Fig. 18; 34, 32, and 38) comprise: an insulating layer (32; [0054]) having a surface (bottom surface) that faces the semiconductor chip (12); and a metal layer (34; [0054]) arranged on the surface (bottom surface) of the insulating layer (32) that faces the semiconductor chip (12), and wherein the first end (adjacent to 144) of the first lead (14) is connected to the metal layer (34); [claim 7] further comprising: a second substrate (Fig. 18; 20; [0053]) spaced apart from the first substrate (30) in the first direction (vertical direction), wherein the semiconductor chip (12) is positioned between the first substrate (30) and the second substrate (20); and a second lead (Fig. 22; 15; [0108]) that extends in the first direction (15 is three-dimensional and extends in all 3 orthogonal directions, including the first/vertical direction), the second lead (15) having (i) a first end (adjacent to 164; [0111]) electrically connected (through 164; [0111]) to the second substrate (20; [0111]) and (ii) a second end (outside of 11) exposed to the outside; [claim 8] wherein the second end (Fig. 22; outside of 11) of the first lead (14) and the second end (outside of 11) of the second lead (15) are connected to different external terminals (14 is connected to the positive electrode of external power supply and 15 is connected to the negative electrode of external power supply, which are two different terminals/electrodes; [0108]), respectively; [claim 9] wherein the different external terminals are a P terminal and an N terminal, respectively (Examiner interprets a “P terminal” to be the positive electrode/terminal and “N terminal” to be the negative electrode/terminal, 14 is connected to the positive electrode of external power supply and 15 is connected to the negative electrode of external power supply; [0108]); [claim 10] wherein the second end (Fig. 22; outside of 11) of the first lead (14) and the second end (outside of 11) of the second lead (15) are disposed at one side (right side) relative to the semiconductor chip (12) in the second direction (horizontal direction); [claim 12] further comprising: a third lead (Fig. 18; 18; [0108]) that extends in the second direction (horizontal direction), the third lead (18) having (i) a first end (adjacent to 48; [0058]) connected to at least one of the first substrate or the second substrate (20) and (ii) a second end (outside of 11) exposed to the outside; [claim 13] wherein the second end (Fig. 18; outside of 11) of the third lead (18) protrudes to the outside in the second direction (horizontal direction); [claim 14] wherein the first lead (Fig. 22; 14) and the third lead (18) are connected to different external terminals (14 is connected to the positive electrode/terminal of external power supply and 18 is connected to a terminal of a control board; [0108]), respectively; [claim 15] wherein the first lead (Fig. 22; 14) and the third lead (18) are disposed at opposite sides (right and left sides, respectively) with respect to the semiconductor chip (12) in the second direction (horizontal direction).
Allowable Subject Matter
Claims 4, 5, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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