DETAILED ACTION
This correspondence is in response to the communications received July 22, 2026. Claims 1-6, 8-21 and 23-32 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant has elected Species II in the response to the restriction requirement dated May 22, 2026. Claims 7 and 22 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species I, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on July 22, 2026. Applicant's election with traverse of the restriction between Species I and II in the reply filed, is acknowledged. The traversal is on the ground(s) that claims 1-6, 8-21 and 23-32 are generic to both species, however, this is not found persuasive because, this argument does not address the reason why the basis for restriction is incorrect and thus does not distinctly and specifically point out supposed errors in the election of species requirement. Further, a serious search burden exists in the examination of the two mutually exclusive identified species, which would include further separate consideration and development of field of search, for the examination of both species.
The requirement is still deemed proper and is therefore made FINAL.
Relevant Prior Art
Sugawara (US 2025/0070003) Fig. 1, shown below. ¶ 0042, “The outer diameter of the second conductor portion 82 is smaller than the outer diameter of the upper pad of the first conductor portion 81.”
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1, an integrated device comprising:
a die substrate (102, ¶ 0031);
a die interconnection (104, ¶ 0031) coupled to the die substrate (coupled to 102);
an encapsulation layer (112, ¶ 0032) coupled to a side surface of the die substrate (coupled to side of 102) and a side surface of the die interconnection (coupled to side of 104);
a plurality of pad interconnects (“pad interconnects 101”, ¶ 0031 n ) coupled to the die interconnection (coupled to 104);
a passivation layer (106, ¶ 0032) coupled to the die interconnection (106 coupled to 104); and
a plurality of metallization interconnects (105, ¶ 0034),
wherein one or more metallization interconnects (105) from the plurality of metallization interconnects is coupled to one or more pad interconnects (101, ¶ 0031) from the plurality of pad interconnects (plural 101 shown),
wherein the plurality of metallization interconnects (105) comprise a first step pad interconnect structure (“the plurality of metallization interconnects 105 to form the step pad interconnects, helps provide additional surface area (e.g., wall surface area, Z-direction surface) for solder to couple to, and is thus less likely to spread out and (unintentionally) couple to other nearby pad interconnects.”, ¶ 0033).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 28-32 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan et al. (US 9,576,919) in view of Yang et al. (US 2021/0098398) in view of Jang et al. (US 2024/0387421).
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Regarding claim 1, the prior art of Scanlan discloses in Figs. 11 and 13, an integrated device (“semiconductor die 24”, is stated to contain circuits which could be integrated circuits including an ‘ASIC’, see col. 8, line 62 to col. 9, line 5, where ‘ASIC’ means, “application specific integrated circuits (ASIC)”, col. 8 line 14.) comprising:
a die substrate (“individual semiconductor die 24”, col. 8, lines 58-59);
an encapsulation layer (“encapsulant 182”, col. 23, line 29) coupled to a side surface of the die substrate (182 on side surface of 24);
a plurality of pad interconnects (“electrically conductive layer 32”, col. 9, line 9);
a passivation layer (“passivation layer 36”, col. 9, lines 36-37); and
a plurality of metallization interconnects (“RDL traces 40”, col. 9, line 60),
wherein one or more metallization interconnects (40) from the plurality of metallization interconnects is coupled to one or more pad interconnects from the plurality of pad interconnects (plural 40 couple to plural 32).
First, Scanlan does not specifically disclose the feature of, “a die interconnection”, and thus does not disclose,
“a die interconnection coupled to the die substrate;
an encapsulation layer coupled to … a side surface of the die interconnection;
a plurality of pad interconnects coupled to the die interconnection;
a passivation layer coupled to the die interconnection”.
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Yang discloses in Figs. 7-19B,
a die interconnection (“interconnect structure 106”, ¶ 0019, Fig. 8) coupled to the die substrate (“semiconductor body 702 comprises a plurality of integrated chip die regions 704-706. A plurality of transistor devices 104 are formed along a first side 702si (e.g., a front-side) of the semiconductor body 702 within each of the plurality of integrated chip die regions 704-706.”, ¶ 0051);
an encapsulation layer (Scanlan’s equivalent encapsulation 182 would be positioned in the place where Yang’s cover 120, ¶ 0021 is located. See further explanation below.) coupled to … a side surface of the die interconnection (side surface of 106);
a plurality of pad interconnects (“bond pad structure 112”, ¶ 0020, see Fig. 12) coupled to the die interconnection (112 connect to “interconnect layers 108”, ¶ 0020, in 106);
a passivation layer (“passivation layer 204”, ¶ 0028, Fig. 9) coupled to the die interconnection (204 couples to 106, see Fig. 9).
The “interconnect structure 106”, ¶ 0028 equates to the interlevel metallization which is a back end of the line (BEOL) construct that connects the internal integrated devices (such as the transistors 104 in 702, ¶ 0051, Fig. 7) to the externally oriented electrical pads of the chip (such as “bond pad structure 112”, ¶ 0020, Fig. 12), which the pads are ultimately used to electrically connect the chip at the packaging level. The use of a BEOL interlevel metallization on an active integrated circuit chip is a well known and common practice in the art. What Scanlan does not disclose in Fig. 11, are the details of an integrated circuit chip which has the active devices on the semiconductor substrate, and then the wiring construction of the interlevel metallization back end of the line (BEOL) wiring that then bridges the electrical connection of the active devices to the externally oriented electrodes (Scanlan’s external chip pads 32) which are the analogous “pad interconnects”. Yang bridges this by disclosing the intermediate interlevel metallization back end of the line (BEOL) that connects the active devices to the externally oriented electrodes that are analogous to the “pad interconnects”.
Therefore, since Yang shows in Fig. 19B, where side surfaces of equivalent “die interconnection” (106) are exposed and subsequently covered by a covering, then the teaching of the presence of an equivalent “die interconnection” by Yang, would then place this feature in direct connection to Scanlan Fig. 11’s “encapsulant 182”, col. 23, line 29. This teaching would then lead to satisfying the limitation of, “an encapsulation layer coupled to … a side surface of the die interconnection”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a die interconnection coupled to the die substrate;
an encapsulation layer coupled to … a side surface of the die interconnection;
a plurality of pad interconnects coupled to the die interconnection;
a passivation layer coupled to the die interconnection”, as disclosed by Yang in the system of Scanlan, for the purpose of provides a means to electrically connect from external to the chip to the internal devices within the chip. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Scanlan does not disclose, “wherein the plurality of metallization interconnects comprise a first step pad interconnect structure.”
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Jang discloses in Figs. 1, 3 and 4, wherein the plurality of metallization interconnects (the feature of “plurality of metallization interconnects” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036, “redistribution pattern 235”, ¶ 0047, and “first seed layer pattern 233.”, ¶ 0060) comprise a first step pad interconnect structure (the portion interpreted as the “first step pad interconnect structure” of the above interpreted “plurality of metallization interconnects”, which is the cross section profile of 250 on 236, creates a shape that resembles a “step” shape, due to the diameter D2 being smaller than the diameter of D1, see Fig. 3). The purpose of this configuration is set forth in ¶ 0011, “Accordingly, an edge portion of the UBM pad may not overlap the protective layer, but may be bonded to the protrusion pattern of the underlying redistribution wiring. Since the UBM pad has a metal-metal bond with the protrusion pattern, an edge peeling-off defect due to a difference in a thermal expansion coefficient may be prevented to thereby improve board level reliability.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “wherein the plurality of metallization interconnects comprise a first step pad interconnect structure”, as disclosed by Jang in the system of Scanlan, for the purpose of bolstering the electrode adhesion connection and improve reliability of the electrical connections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Scanlan et al. disclose the integrated device of claim 1, and Jang discloses in Figs. 1, 3 and 4, wherein the first step pad interconnect structure (the feature of “first step pad interconnect structure” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprises:
a first pad interconnect (“under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprising a first diameter (“second diameter D2”, ¶ 0042); and
a second pad interconnect (“protrusion pattern 236”, ¶ 0036) comprising a second diameter (“first diameter D1”, ¶ 0042) that is different from the first diameter (“first diameter D1 of the protrusion pattern 236 may be greater than a second diameter D2 of the UBM pad 250”, ¶ 0042, see Figs. 3 and 4).
Regarding claim 3, the prior art of Scanlan et al. disclose the integrated device of claim 1, and Jang discloses in Figs. 1, 3 and 4, further comprising a solder interconnect (“the conductive bump 300 may include a solder bump or a solder ball.”, ¶ 0044) coupled to the first step pad interconnect structure (300 connected to 250/236).
Regarding claim 4, the prior art of Scanlan et al. disclose the integrated device of claim 1, and Jang discloses in Figs. 1, 3 and 4, wherein the plurality of metallization interconnects (the feature of “plurality of metallization interconnects” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036, “redistribution pattern 235”, ¶ 0047, and “first seed layer pattern 233.”, ¶ 0060) comprises a trace metallization interconnect (“redistribution pattern 235”, ¶ 0047) coupled to and touching the first step pad interconnect structure (235 couples to 250/236).
Regarding claim 5, the prior art of Scanlan et al. disclose the integrated device of claim 1, and Jang discloses in Figs. 1, 3 and 4, wherein the plurality of metallization interconnects (the feature of “plurality of metallization interconnects” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036, “redistribution pattern 235”, ¶ 0047, and “first seed layer pattern 233.”, ¶ 0060) comprises a via metallization interconnect (portion of 235/233 that resides in “first openings 211”, ¶ 0056) coupled to and touching the first step pad interconnect structure (235/233 couple to 250/236).
Regarding claim 28, the prior art of Scanlan discloses in Figs. 11 and 13, a device (see title, “Semiconductor Device …”) comprising:
a die substrate (“individual semiconductor die 24”, col. 8, lines 58-59);
an encapsulation layer (“encapsulant 182”, col. 23, line 29) coupled to a side surface of the die substrate (182 on side surface of 24);
a plurality of pad interconnects (“electrically conductive layer 32”, col. 9, line 9);
a passivation layer (“passivation layer 36”, col. 9, lines 36-37); and
a plurality of metallization interconnects (“RDL traces 40”, col. 9, line 60),
wherein one or more metallization interconnects (40) from the plurality of metallization interconnects is coupled to one or more pad interconnects from the plurality of pad interconnects (plural 40 couple to plural 32).
First, Scanlan does not disclose, the feature of the “a die interconnection”, and therefore does not disclose,
“a die interconnection coupled to the die substrate;
an encapsulation layer coupled to … a side surface of the die interconnection;
a plurality of pad interconnects coupled to the die interconnection;
a passivation layer coupled to the die interconnection”.
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Yang discloses in Figs. 7-19B,
a die interconnection (“interconnect structure 106”, ¶ 0019, Fig. 8) coupled to the die substrate (“semiconductor body 702 comprises a plurality of integrated chip die regions 704-706. A plurality of transistor devices 104 are formed along a first side 702si (e.g., a front-side) of the semiconductor body 702 within each of the plurality of integrated chip die regions 704-706.”, ¶ 0051);
an encapsulation layer (Scanlan’s equivalent encapsulation 182 would be positioned in the place where Yang’s cover 120, ¶ 0021 is located. See further explanation below.) coupled to … a side surface of the die interconnection (side surface of 106);
a plurality of pad interconnects (“bond pad structure 112”, ¶ 0020, see Fig. 12) coupled to the die interconnection (112 connect to “interconnect layers 108”, ¶ 0020, in 106);
a passivation layer (“passivation layer 204”, ¶ 0028, Fig. 9) coupled to the die interconnection (204 couples to 106, see Fig. 9).
The “interconnect structure 106”, ¶ 0028 equates to the interlevel metallization which is a back end of the line (BEOL) construct that connects the internal integrated devices (such as the transistors 104 in 702, ¶ 0051, Fig. 7) to the externally oriented electrical pads of the chip (such as “bond pad structure 112”, ¶ 0020, Fig. 12), which the pads are ultimately used to electrically connect the chip at the packaging level. The use of a BEOL interlevel metallization on an active integrated circuit chip is a well known and common practice in the art. What Scanlan does not disclose in Fig. 11, are the details of an integrated circuit chip which has the active devices on the semiconductor substrate, and then the wiring construction of the interlevel metallization back end of the line (BEOL) wiring that then bridges the electrical connection of the active devices to the externally oriented electrodes (Scanlan’s external chip pads 32) which are the analogous “pad interconnects”. Yang bridges this by disclosing the intermediate interlevel metallization back end of the line (BEOL) that connects the active devices to the externally oriented electrodes that are analogous to the “pad interconnects”.
Therefore, since Yang shows in Fig. 19B, where side surfaces of equivalent “die interconnection” (106) are exposed and subsequently covered by a covering, then the teaching of the presence of an equivalent “die interconnection” by Yang, would then place this feature in direct connection to Scanlan Fig. 11’s “encapsulant 182”, col. 23, line 29. This teaching would then lead to satisfying the limitation of, “an encapsulation layer coupled to … a side surface of the die interconnection”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a die interconnection coupled to the die substrate;
an encapsulation layer coupled to … a side surface of the die interconnection;
a plurality of pad interconnects coupled to the die interconnection;
a passivation layer coupled to the die interconnection”, as disclosed by Yang in the system of Scanlan, for the purpose of provides a means to electrically connect from external to the chip to the internal devices within the chip. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Scanlan does not disclose, “wherein the plurality of metallization interconnects comprise a first step pad interconnect structure.”
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Jang discloses in Figs. 1, 3 and 4, wherein the plurality of metallization interconnects (the feature of “plurality of metallization interconnects” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036, “redistribution pattern 235”, ¶ 0047, and “first seed layer pattern 233.”, ¶ 0060) comprise a first step pad interconnect structure (the cross section profile of 250 on 236, creates a shape that resembles a “step” shape, due to the diameter D2 being smaller than the diameter of D1, see Fig. 3). The purpose of this configuration is set forth in ¶ 0011, “Accordingly, an edge portion of the UBM pad may not overlap the protective layer, but may be bonded to the protrusion pattern of the underlying redistribution wiring. Since the UBM pad has a metal-metal bond with the protrusion pattern, an edge peeling-off defect due to a difference in a thermal expansion coefficient may be prevented to thereby improve board level reliability.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “wherein the plurality of metallization interconnects comprise a first step pad interconnect structure”, as disclosed by Jang in the system of Scanlan, for the purpose of bolstering the electrode adhesion connection and improve reliability of the electrical connections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 29, the prior art of Scanlan et al. disclose the integrated device of claim 28, and Jang discloses in Figs. 1, 3 and 4, wherein the first step pad interconnect structure (the feature of “first step pad interconnect structure” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprises:
a first pad interconnect (“under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprising a first diameter (“second diameter D2”, ¶ 0042); and
a second pad interconnect (“protrusion pattern 236”, ¶ 0036) comprising a second diameter (“first diameter D1”, ¶ 0042) that is different from the first diameter (“first diameter D1 of the protrusion pattern 236 may be greater than a second diameter D2 of the UBM pad 250”, ¶ 0042, see Figs. 3 and 4).
Regarding claim 30, the prior art of Scanlan et al. disclose the integrated device of claim 28, and Jang discloses in Figs. 1, 3 and 4, further comprising a solder interconnect (“the conductive bump 300 may include a solder bump or a solder ball.”, ¶ 0044) coupled to the first step pad interconnect structure (300 connected to 250/236).
Regarding claim 31, the prior art of Scanlan et al. disclose the integrated device of claim 28, and Jang discloses in Figs. 1, 3 and 4, wherein the plurality of metallization interconnects (the feature of “plurality of metallization interconnects” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036, “redistribution pattern 235”, ¶ 0047, and “first seed layer pattern 233.”, ¶ 0060) comprises a trace metallization interconnect (“redistribution pattern 235”, ¶ 0047) coupled to and touching the first step pad interconnect structure (235 couples to 250/236).
Regarding claim 32, the prior art of Scanlan et al. disclose the integrated device of claim 28, wherein the device comprises a die, a passive device, or an interposer (Scanlan discloses “individual semiconductor die 24”, col. 8, lines 58-59).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Scanlan et al. (US 9,576,919) in view of Yang et al. (US 2021/0098398) in view of Jang et al. (US 2024/0387421) in view of Chang et al. (US 2021/0096310).
Regarding claim 6, the prior art of Scanlan et al. disclose the integrated device of claim 1, however Scanlan does not disclose,
“wherein the plurality of metallization interconnects comprises:
a first trace metallization interconnect coupled to the first step pad interconnect structure; and
a second step pad interconnect structure coupled to the first trace metallization interconnect.”
Jang already teaches the “step pad interconnect structure” in the rejection of claim 1, so what is not shown are that one trace has plural step pad interconnect structures.
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Chang discloses in Fig. 2C, where one trace (annotated ‘trace’) has two interconnect structures (annotated ‘interconnect structures’), which then combined with Jang’s “step pad interconnect structure”, would then satisfy the limitation of this claim, where a second step pad interconnect could be utilized on a single trace.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “wherein the plurality of metallization interconnects comprises:
a first trace metallization interconnect coupled to the first step pad interconnect structure; and
a second step pad interconnect structure coupled to the first trace metallization interconnect.”, as disclosed by Chang/Jang in the system of Scanlan, for the purpose of making a connection orientation which can route the signal from one trace to two different pathways which can utilize the same signal in two different circuits. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan et al. (US 9,576,919) in view of Yang et al. (US 2021/0098398) in view of Jang et al. (US 2024/0387421) in view of Chiu et al. (US 2011/0248404).
Regarding claim 8, the prior art of Scanlan et al. disclose the integrated device of claim 1, however Scanlan does not disclose, “further comprising a plurality of back side metallization interconnects.”
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Chiu discloses in Fig. 3, further comprising a plurality of back side metallization interconnects (the metallization elements within 60, “backside interconnect structure 60”, ¶ 0020).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “further comprising a plurality of back side metallization interconnects”, as disclosed by Chiu in the system of Scanlan, for the purpose of including further electrical interconnections of additional device circuitry which can expand the device functionality of the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 9, the prior art of Scanlan et al. disclose the integrated device of claim 8, and Chiu does not disclose, “wherein the plurality of back side metallization interconnects comprise a second step pad interconnect structure.”
Jang discloses in Figs. 1, 3 and 4 the use of metallization interconnects comprise a second step pad interconnect structure (on of plurality of portions 250/236 of the feature of “plurality of metallization interconnects” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036, “redistribution pattern 235”, ¶ 0047, and “first seed layer pattern 233.”, ¶ 0060). Then utilizing these “step pad metallization interconnects” in place of Chiu’s Fig. 3 element 76, would result in satisfying the limitation of the claim.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “wherein the plurality of back side metallization interconnects comprise a second step pad interconnect structure”, as disclosed by Chiu in the system of Scanlan, for the purpose of including further electrical interconnections of additional device circuitry which can expand the device functionality of the overall device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 10, the prior art of Scanlan et al. disclose the integrated device of claim 8, and Chiu discloses in Fig. 3, further comprising a plurality of through substrate vias (“TSV 20A”, ¶ 0020) located in the die substrate (12, ¶ 0017, the die aspect has already been disclosed in the rejection of claim 1), wherein one or more through substrate vias (20A) from the plurality of through substrate vias is coupled to one or more back side metallization interconnects (“backside interconnect structure 60”, ¶ 0020) from the plurality of back side metallization interconnects (plural 60 shown).
Claims 11, 12, 13, 15-19 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan et al. (US 9,576,919) in view of Yang et al. (US 2021/0098398) in view of Jang et al. (US 2024/0387421) in view of Gandhi et al. (US 2020/0035635).
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Regarding claim 11, the prior art of Scanlan discloses in Figs. 11 and 13, a package structure (“FIG. 11 shows an individual semiconductor package”, col. 29, line 3) comprising:
a first integrated device (collection of components which will be disclosed below) comprising:
a first die substrate (“individual semiconductor die 24”, col. 8, lines 58-59);
a first encapsulation layer (“encapsulant 182”, col. 23, line 29) coupled to a side surface of the first die substrate (182 on side surface of 24);
a first plurality of pad interconnects (“electrically conductive layer 32”, col. 9, line 9);
a passivation layer (“passivation layer 36”, col. 9, lines 36-37);
a first plurality of metallization interconnects (“RDL traces 40”, col. 9, line 60),
wherein one or more metallization interconnects from the first plurality of metallization interconnects is coupled to one or more pad interconnects from the first plurality of pad interconnects (40 couple to 32, Fig. 11).
First, Scanlan does not specifically disclose the feature of, “a first die interconnection”, and thus does not disclose,
“a first die interconnection coupled to the first die substrate;
a first encapsulation layer coupled to a side surface of the first die substrate and a side surface of the first die interconnection;
a first plurality of pad interconnects coupled to the first die interconnection;
a passivation layer coupled to the first die interconnection”.
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Yang discloses in Figs. 7-19B,
a first die interconnection (“interconnect structure 106”, ¶ 0019, Fig. 8) coupled to the first die substrate (“semiconductor body 702 comprises a plurality of integrated chip die regions 704-706. A plurality of transistor devices 104 are formed along a first side 702si (e.g., a front-side) of the semiconductor body 702 within each of the plurality of integrated chip die regions 704-706.”, ¶ 0051);
a first encapsulation layer (Scanlan’s equivalent encapsulation 182 would be positioned in the place where Yang’s cover 120, ¶ 0021 is located. See further explanation below.) coupled to … a side surface of the first die interconnection (side surface of 106);
a first plurality of pad interconnects (“bond pad structure 112”, ¶ 0020, see Fig. 12) coupled to the first die interconnection (112 connect to “interconnect layers 108”, ¶ 0020, in 106);
a passivation layer (“passivation layer 204”, ¶ 0028, Fig. 9) coupled to the first die interconnection (204 couples to 106, see Fig. 9).
The “interconnect structure 106”, ¶ 0028 equates to the interlevel metallization which is a back end of the line (BEOL) construct that connects the internal integrated devices (such as the transistors 104 in 702, ¶ 0051, Fig. 7) to the externally oriented electrical pads of the chip (such as “bond pad structure 112”, ¶ 0020, Fig. 12), which the pads are ultimately used to electrically connect the chip at the packaging level. What Scanlan does not disclose in Fig. 11, are the details of an integrated circuit chip which has the active devices on the semiconductor substrate, and then the wiring construction of the interlevel metallization back end of the line (BEOL) wiring that then bridges the electrical connection of the active devices to the externally oriented electrodes (Scanlan’s external chip pads 32) which are the analogous “pad interconnects”. Yang bridges this by disclosing the intermediate interlevel metallization back end of the line (BEOL) that connects the active devices to the externally oriented electrodes that are analogous to the “pad interconnects”.
Therefore, since Yang shows in Fig. 19B, where side surfaces of equivalent “die interconnection” (106) are exposed and subsequently covered by a covering, then the teaching of the presence of an equivalent “die interconnection” by Yang, would then place this feature in direct connection to Scanlan Fig. 11’s “encapsulant 182”, col. 23, line 29. This teaching would then lead to satisfying the limitation of, “an encapsulation layer coupled to … a side surface of the die interconnection”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a die interconnection coupled to the die substrate;
a plurality of pad interconnects coupled to the die interconnection;
a passivation layer coupled to the die interconnection”, as disclosed by Yang in the system of Scanlan, for the purpose of provides a means to electrically connect from external to the chip to the internal devices within the chip. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Scanlan does not disclose, “wherein the first plurality of metallization interconnects comprise a first step pad interconnect structure”.
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Jang discloses in Figs. 1, 3 and 4, wherein the first plurality of metallization interconnects (interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, and “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprise a first step pad interconnect structure (the cross section profile of 250 on 236, creates a shape that resembles a “step” shape, due to the diameter D2 being smaller than the diameter of D1, see Fig. 3). The purpose of this configuration is set forth in ¶ 0011, “Accordingly, an edge portion of the UBM pad may not overlap the protective layer, but may be bonded to the protrusion pattern of the underlying redistribution wiring. Since the UBM pad has a metal-metal bond with the protrusion pattern, an edge peeling-off defect due to a difference in a thermal expansion coefficient may be prevented to thereby improve board level reliability.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “wherein the first plurality of metallization interconnects comprise a first step pad interconnect structure”, as disclosed by Jang in the system of Scanlan, for the purpose of bolstering the electrode adhesion connection and improve reliability of the electrical connections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Scanlan does not disclose, “a second integrated device coupled to the first integrated device through at least a first plurality of solder interconnects.”
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Gandhi discloses in Figs. 2G-2H, a second integrated device (“second IC die 282”, ¶ 0030) coupled to the first integrated device (“first IC die 264”, ¶ 0030) through at least a first plurality of solder interconnects (“solder balls 218”, ¶ 0030, then after reflow, “solder interconnect 276”, ¶ 0030).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “a second integrated device coupled to the first integrated device through at least a first plurality of solder interconnects”, as disclosed by Gandhi in the system of Scanlan, for the purpose of stacking integrated circuit chips to increase the overall device functionality by expanding the capacity of the system. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 12, the prior art of Scanlan et al. disclose the integrated device of claim 11, and Jang discloses in Figs. 1, 3 and 4, wherein the first step pad interconnect structure (the feature of “first step pad interconnect structure” is interpreted as the combination of features of “protrusion pattern 236”, ¶ 0036, “under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprises:
a first pad interconnect (“under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprising a first diameter (“second diameter D2”, ¶ 0042); and
a second pad interconnect (“protrusion pattern 236”, ¶ 0036) comprising a second diameter (“first diameter D1”, ¶ 0042) that is different from the first diameter (“first diameter D1 of the protrusion pattern 236 may be greater than a second diameter D2 of the UBM pad 250”, ¶ 0042, see Figs. 3 and 4).
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Regarding claim 13, the prior art of Scanlan et al. disclose the integrated device of claim 11, and Gandhi discloses in Figs. 2G-2H, wherein the second integrated device (“second IC die 282”, ¶ 0030) comprises a second plurality of metallization interconnects (“layer 228”, ¶ 0019). Gandhi does show that the metallization interconnects (228) are the same, but not in the configuration as shown by Jang, which already shows the details of the “step pad interconnect structure” in the rejection of claim 11. So by combining the teaching of the step pad interconnect of Jang as shown in the rejection of claim 11, the limitation of, “wherein the second plurality of metallization interconnects comprises a second step pad interconnect structure”, would then be satisfied.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the limitation of, “wherein the second plurality of metallization interconnects comprises a second step pad interconnect structure”, as disclosed by Jang in the system of Scanlan, for the purpose of bolstering the electrode adhesion connection and improve reliability of the electrical connections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 15, the prior art of Scanlan et al. disclose the integrated device of claim 13, and Gandhi discloses in Figs. 2G-2H, in the modified construction as set forth in the rejection of claim 13, where the “step pad interconnect structure” would modify the 228 of both opposing chips in Fig. 2G-2H, would then satisfy,
wherein the second step pad interconnect structure comprises:
a first pad interconnect (“under bump metallurgy (UBM) pad 250 is disposed”, ¶ 0036) comprising a first radius (“second diameter D2”, ¶ 0042); and
a second pad interconnect (“protrusion pattern 236”, ¶ 0036) comprising a second radius (“first diameter D1”, ¶ 0042) that is different from the first radius (“first diameter D1 of the protrusion pattern 236 may be greater than a second diameter D2 of the UBM pad 250”, ¶ 0042, see Figs. 3 and 4).
Regarding claim 16, the prior art of Scanlan et al. disclose the integrated device of claim 11, and Gandhi discloses in Figs. 2G-2H and further in Fig. 5, wherein the first integrated device (“IC die 264”, ¶ 0022) comprises a first front side and a first back side (in Fig. 5, 264 has front side and backside), and
wherein the second integrated device (“IC die 282”, ¶ 0029) comprises a second front side and a second back side (in Fig. 5, 282 has front side and backside).
Regarding claim 17, the prior art of Scanlan et al. disclose the integrated device of claim 16, and Gandhi discloses in Fig. 5, wherein the first front side of the first integrated device is coupled to the second front side of the second integrated device through at least the first plurality of solder interconnects (both front and back sides of 264 are either directly or indirectly connected to front and/or back sides of 282).
Regarding claim 18, the prior art of Scanlan et al. disclose the integrated device of claim 16, and Gandhi discloses in Fig. 5, wherein the first front side of the first integrated device is coupled to the second back side of the second integrated device through at least the first plurality of solder interconnects (both front and back sides of 264 are either directly or indirectly connected to front and/or back sides of 282).
Regarding claim 19, the prior art of Scanlan et al. disclose the integrated device of claim 11, and Jang discloses in Figs. 1, 3 and 4, wherein a solder interconnect (“the conductive bump 300 may include a solder bump or a solder ball.”, ¶ 0044) from the first plurality of solder interconnects is coupled to the first step pad interconnect structure (300 connected to 250/236).
Regarding claim 27, the prior art of Scanlan et al. disclose the integrated device of claim 11, wherein the package is part of a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Scanlan discloses the device disclosed can be used in various capacities that satisfy the limitation of the claim, col. 8, lines 4-20).
Allowable Subject Matter
Claims 14 and 20-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 21-26 are objected to due to their dependence upon claim 20.
The prior art of Scanlan et al. (US 9,576,919) et al. fail to disclose the full details of the “second plurality of metallization interconnects”, thus even though the Gandhi et al. (US 2020/0035635) reference teaches matching opposing electrode configurations in Figs. 2G-2H, the full details are not presented in the prior art that extend to the electrode configuration of a “second integrated device” (from claim 13 upon which claim 14 depends). This stands separate and distinct from the determination that within the same package the electrical configuration would be obvious to utilize throughout the integrated device as set forth in claim 11.
“14. (Original) The package of claim 13, wherein the second plurality of metallization interconnects comprises a plurality of back side metallization interconnects, and wherein the second step pad interconnect structure is part of the plurality of back side metallization interconnects.”
The same reasoning applies to the objection of claim 14 applies to the objection of claim 20, which further details the electrical configuration for a “second integrated device”, where even though the Gandhi et al. (US 2020/0035635) reference teaches matching opposing electrode configurations in Figs. 2G-2H, the full details are not presented in the prior art that extend to the electrode configuration of a “second integrated device” of claim 20, as detailed below.
“20. (Original) The package of claim 11, wherein the second integrated device comprises:
a second die substrate;
a second die interconnection coupled to the second die substrate;
…
a second plurality of pad interconnects coupled to the second die interconnection; and
a second plurality of metallization interconnects coupled to the second plurality of pad interconnects,
wherein the second plurality of metallization interconnects comprises a second step pad interconnect structure.”
Contact Information
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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