CTNF 18/611,488 CTNF 77798 DETAILED ACTION Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In lines 1-2 of claim 2, the applicant states “each pad of the plurality of pads has a uniform width in a vertical direction.”; however, in lines 19-20 of claim 1, the applicant states “a surface flatness of a top surface of the pad layer is greater than a surface flatness of a bottom surface of the pad layer.” Since claim 2 is dependent on claim 1, the claims appear contradictory to each other since it is unknown how a pad layer with different surface flatness at the top and bottom surface can have uniform width in a vertical direction. The same applies to claim 17, which has a similar limitation. Appropriate clarification and/or correction are required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 thru 3, and 10 thru 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. US 2021/0050327 A1 in view of Lee et al. US 2019/0131221 A1. Lee discloses (see, for example, FIG. 14) a semiconductor package 1a comprising a first redistribution layer 700, bridge chip 101, mold layer 550, second redistribution layer 900, conductive post 510, first semiconductor chip 11, pad layer 718/802, interconnection layer 714, first insulating layer 802, and plurality of pads 718. The top surfaces of the plurality of pads 718 are exposed to an outside of the first insulating layer 802 near a top surface of the first insulating layer 802, and the bottom surfaces of the plurality of pads 718 are exposed to the outside of the first insulating layer 802 near a bottom surface of the first insulating layer 802. Lee does not disclose a surface flatness of a top surface of the pad layer being greater than a surface flatness of a bottom surface of the pad layer. However, Lee discloses (see, for example, FIG. 12B) a pad layer 142b having a surface flatness of at top surface of the pad layer being greater than a surface flatness of a bottom surface of the pad layer 142b. In paragraph [0103], Lee discloses the bottom surface having recesses R1, R2, R3 that increase contact area and, hence, the connection reliability. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a surface flatness of a top surface of the pad layer being greater than a surface flatness of a bottom surface of the pad layer in order to increase contact area and, hence the connection reliability . Regarding claim 2, see, for example, FIG. 14 wherein Shih discloses each pad 718 of the plurality of pads having a uniform width in a vertical direction. Also see 112 rejection above. Regarding claim 3, Shih in view of Lee does not expressly disclose a total thickness variation of the pad layer ranging from 0 um to 10 um; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a total thickness variation of the pad layer ranging from 0 um to 10 um in order to maintain a uniform surface for ensuring a stable connection, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 10, Shih in view of Lee does not clearly disclose the plurality of pads having a thickness ranging from 5 um to 20 um, and wherein a distance between two adjacent pads of the plurality of pads ranges from 10 um to 150 um; however, it would have been obvious to one of ordinary skill in the art to have the plurality of pads having a thickness ranging from 5 um to 20 um, and wherein a distance between two adjacent pads of the plurality of pads ranges from 10 um to 150 um in order to provide a solid base for the solder ball while leaving enough space therebetween to prevent contact, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Regarding claim 11, see, for example, FIG. 14 wherein Shih discloses the pads 718 being coplanar to the first insulating layer 802 on both surfaces. Regarding claim 12, see, for example, FIG. 14 wherein Shih discloses an inactive surface of the bridge chip 101 being attached to the top surface of the first redistribution layer 700, and wherein the bridge chip 101 comprises a plurality of bumps 210 on a top surface of the bridge chip 101. Regarding claim 13, see, for example, FIG. 14 wherein Shih discloses a top surface of the conductive post 510, a top surface of the mold layer 550, and a plurality of top surfaces of the plurality of bumps 210 being substantially flat and are coplanar with each other . 07-22-aia AIA Claim (s) 4 thru 9, 15 thru 19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. US 2021/0050327 A1 in view of Lee et al. US 2019/0131221 A1 as applied to claim 1-3, and 10-13 above, and further in view of Chen et al. US 2014/0103488 A1. Shih in view of Lee does not disclose the interconnection layer comprises: a second insulating layer covering the first insulating layer and the plurality of pads; and an interconnection pattern that is disposed on the second insulating layer, that extends through the second insulating layer, and that is coupled to the plurality of pads. However, Chen discloses (see, for example, Fig. 10) a semiconductor package 66 comprising an interconnection pattern comprising a second insulating layer (i.e. second layer 44 from the top of the four-layer stack of layers 44 shown at the bottom of Fig. 10), first insulating layer (i.e. third layer 44 from the top of the four-layer stack of layers 44 shown at the bottom of Fig. 10), plurality of pads (i.e. metal layer 42 in the third layer 44 from the top of the four-layer stack of layers 44 shown at the bottom of Fig. 10) 42, and an interconnection pattern (i.e. metal layer 42 in top layer 44 of the four-layer stack of layers 44 shown at the bottom of Fig. 10 and the metal layer 42 in the second layer 44 of the four-layer stack of layers 44 shown at the bottom of Fig. 10) that is disposed on the second insulating layer (i.e. second layer 44 from the top of the four-layer stack of layers 44 shown at the bottom of Fig. 10), that extends through the second insulating layer 44, and that is coupled to the plurality of pads 42. It would have been obvious to one of ordinary skill in the art , at a time prior to the effective filing date, to have the interconnection layer comprises: a second insulating layer covering the first insulating layer and the plurality of pads; and an interconnection pattern that is disposed on the second insulating layer, that extends through the second insulating layer, and that is coupled to the plurality of pads in order to increase routing density within the semiconductor package that ensures better structural reliability and electrical performance . Regarding claim 5, see, for example, FIG. 14 wherein Shih discloses a first insulating layer 802 and a second insulating layer 712. In paragraph [0046], Shih discloses the first insulating layer being a solder mask, which are typically made of polymers, and in paragraph [0043] discloses the second insulating layer may include silicon nitride, etc. Further, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first insulating layer and the second insulating layer comprising different materials from each other in order to improve etching selectivity for forming the pads and the overlying interconnection pad and/or metallizations according to the preferences of the user. Regarding claim 6, Shih in view of Lee in view of Chen does not specifically disclose the first insulating layer comprises an epoxy molding compound (EMC) or an Ajinomoto build-up film (ABF), and wherein the second insulating layer comprises a photoimageable dielectric material; however, it would have been obvious to one of ordinary skill in the art to have the first insulating layer comprises an epoxy molding compound (EMC) or an Ajinomoto build-up film (ABF), and wherein the second insulating layer comprises a photoimageable dielectric material in order to have materials that adequately protect the pads and interconnection layer, and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Regarding claim 7, see, for example, FIG. 14 wherein Shih discloses the conductive post 510 being coupled to a top surface of an interconnection pattern 714. Regarding claim 8, see, for example, Fig. 10 wherein Chen discloses a head portion (i.e. in the top layer 44) 42, and tail portion (i.e. in the second to top layer 44) 42. Regarding claims 9, and 21, see, for example, FIG. 14 wherein Shih discloses the plurality of pads 718 having a thickness that is equal to or smaller than a thickness of the interconnection pattern interconnection pattern 714, and the plurality of pads 718 having a width that is equal to or smaller than a width of the interconnection pattern 714. Regarding claim 15, see, for example, the rejection for claims 4, and 8 above. In FIG. 14, Shih discloses the substrate protection layer 802, and an insulating pattern 712. Further, Shih in view of Lee in view of Chen does not expressly disclose a total thickness variation of the pad layer ranging from 0 um to 10 um; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a total thickness variation of the pad layer ranging from 0 um to 10 um in order to maintain a uniform surface for ensuring a stable connection, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 16, see, for example, FIG. 12B wherein Lee discloses a surface flatness of a top surface of the pad layer 142b being greater than a surface flatness of a bottom surface of the pad layer 142b. Regarding claim 17, see, for example, FIG. 14 wherein Shih discloses each pad 718 of the plurality of pads having a uniform width in a vertical direction. Also see 112 rejection above. Regarding claim 18, see, for example, FIG. 14 wherein Shih discloses the plurality of top surfaces of the plurality of outer pads 718 being exposed to an outside of the substrate protection layer 802 near the top surface of the substrate protection layer 802, and wherein a plurality of bottom surfaces of the plurality of outer pads 802 being exposed to the outside of the substrate protection layer 802 near a bottom surface of the substrate protection layer 802. Regarding claim 19, see, for example, FIG. 14 wherein Shih discloses a substrate protection layer 802 and an insulating pattern 712. In paragraph [0046], Shih discloses the substrate protection layer being a solder mask, which are typically made of polymers, and in paragraph [0043] discloses the insulating pattern may include silicon nitride, etc. Further, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the substrate protection layer and insulating pattern comprising different materials from each other in order to improve etching selectivity for forming the pads and the overlying interconnection pad and/or metallizations according to the preferences of the user . 07-21-aia AIA Claim (s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. US 2021/0050327 A1 in view of Lee et al. US 2019/0131221 A1 in view of Chen et al. US 2014/0103488 A1, as applied to claims 4-9, 15-19, and 21, and further in view of Kwon US 2022/0102256 A1. Lee in view of Chen does not disclose a chip stack including a plurality of second semiconductor chips that are vertically stacked on the top surface of the second redistribution layer and that are horizontally spaced apart from the first semiconductor chip. However, Kwon discloses (see, for example, FIG. 1) a semiconductor package 1 comprising a chip stack 1000 including a plurality of second semiconductor chips 300 that are horizontally spaced apart from a semiconductor chip 500. It would have been obvious to one of ordinary skill in the art to have a chip stack including a plurality of second semiconductor chips that are vertically stacked on the top surface of the second redistribution layer and that are horizontally spaced apart from the first semiconductor chip in order to have a chip that has many functions divided between multiple sub-chips according to the preferences of the user . INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee April 24, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815 Application/Control Number: 18/611,488 Page 2 Art Unit: 2815 Application/Control Number: 18/611,488 Page 3 Art Unit: 2815 Application/Control Number: 18/611,488 Page 4 Art Unit: 2815 Application/Control Number: 18/611,488 Page 5 Art Unit: 2815 Application/Control Number: 18/611,488 Page 6 Art Unit: 2815 Application/Control Number: 18/611,488 Page 7 Art Unit: 2815 Application/Control Number: 18/611,488 Page 8 Art Unit: 2815 Application/Control Number: 18/611,488 Page 9 Art Unit: 2815 Application/Control Number: 18/611,488 Page 10 Art Unit: 2815
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