Prosecution Insights
Last updated: October 02, 2026
Application No. 18/611,728

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Non-Final OA §102§103§112
Filed
Mar 21, 2024
Priority
Apr 13, 2022 — JP 2022-066313 +1 more
Examiner
CHEN, DAVID Z
Art Unit
Tech Center
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
45%
Grant Probability
Moderate
1-2
OA Rounds
1y 0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
308 granted / 689 resolved
-15.3% vs TC avg
Strong +50% interview lift
Without
With
+50.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
51 currently pending
Career history
754
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.1%
+9.1% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
25.1%
-14.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 689 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment/Restriction Applicant’s election without traverse of Invention I, Species XI, Embodiment 11 (Fig. 15: 208, Ztd, and Fig. 9), and Claims 1-7, 9-13, 15, 16, 21, and 24-27 in the reply filed on June 24, 2026 is acknowledged. However, Claims 4-11 appear to read on non-elected embodiments of FIG. 6-FIG. 8. Thus, Claims 4-11, 14, 17-20, and 22-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 24, 2026. Specification The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-3, 12-13, 15-16, 21, and 24-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 1, the limitation “an avalanche breakdown voltage in the diode portion is 0.7 times or more and less than 1 time an avalanche breakdown voltage in the transistor portion” does not specify how the recited property corresponds to the recited physical structures or the recited property is obtained from the intended-use of the recited physical structures. At least [0101], [0104], [0113], [0115], [0120], [0125], [0141], [0156], [0165], [0176] of the Specification disclose different measurements under a specific condition of 25 ºC, different physical intervals, and different doping concentrations that determine the avalanche breakdown voltage. It is not clear how the recited property is obtained without specifying the particular parameters, conditions, structures, and measurements. It is not clear whether there are unlimited possibilities to obtain the recited property by adjusting the parameters, conditions, structures, and measurements that may or may not be supported by the original disclosure. Thus, the limitation render the claims indefinite and clarification is required. Claims 2, 24, and 26-27 are similarly rejected. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3, 12-13, 15-16, and 24-27 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2016/0218101 A1 to Gejo (“Gejo”). As to claim 1, Gejo discloses a semiconductor device comprising: a semiconductor substrate which has an upper surface and a lower surface and is provided with a drift region (24) of a first conductivity type (N); a transistor portion (R1) which includes a collector region (21) of a second conductivity type (P) in contact with the lower surface of the semiconductor substrate and an emitter region (26) of the first conductivity type (N) provided in contact with the upper surface of the semiconductor substrate and having a doping concentration (n++) higher than that (n--) of the drift region (24); and a diode portion (R2) which includes a cathode region (22) of the first conductivity type (N) in contact with the lower surface of the semiconductor substrate, wherein an avalanche breakdown voltage in the diode portion is 0.7 times or more and less than 1 time an avalanche breakdown voltage in the transistor portion (See Fig. 1-Fig. 3, ¶ 0014-¶ 0023, ¶ 0032-¶ 0035) (Notes: the limitation “drift” is met by the conductivity and relative position). As to claim 2, Gejo further discloses wherein a cathode voltage at which the diode portion (R2) reaches a negative resistance region is equal to or larger than a collector voltage at which the transistor portion (R1) reaches a negative resistance region (See Fig. 2, Fig. 3). As to claim 3, Gejo further discloses wherein the diode portion (R2) and the transistor portion (R1) include a plurality of trench portions (at 12, 13, 43), which are arranged at intervals along an array direction, on the upper surface of the semiconductor substrate (See Fig. 2, Fig. 3). As to claim 12, Gejo further discloses wherein at least some (at 12) of the trench portions (12, 13, 43) in the transistor portion (R1) have a first length (above L1) in a depth direction of the semiconductor substrate, and at least some (at 43) of the trench portions (12, 13, 43) in the diode portion (R2) have a second length (above L2) larger than the first length (above L1) in the depth direction (See Fig. 3). As to claim 13, Gejo further discloses comprising an intermediate region (between 12 and 13/43) which is arranged between the diode portion (R2) and the transistor portion (R1), is provided with a plurality of the trench portions (at 12, 13, 43), and includes the cathode region (22) and the collector region (21), wherein the intermediate region (between 12 and 13/73) includes a transistor side region (left) in contact with the transistor portion (R1), and the transistor side region includes the trench portion (at 12, 13, 43) having the first length (above L1) (See Fig. 1, Fig. 3) (Notes: the limitation “region” is defined as any of the major subdivisions into which the body or one of its parts is divisible by Merriam-Webster.com). As to claim 15, Gejo further discloses wherein a boundary position between the cathode region (22) and the collector region (21) in the intermediate region (between 12 and 13/43) is arranged in the transistor side region (left) (See Fig. 1, Fig. 3). As to claim 16, Gejo further discloses wherein a length in the depth direction of the plurality of trench portions (at 12, 13, 43) in the intermediate region (between 12, 13/43) increases when approaching the diode portion (R2) (See Fig. 3). As to claim 24, Gejo discloses further comprising: an intermediate region (between 12 and 13/43) which is arranged between the diode portion (R2) and the transistor portion (R1), is provided with a plurality of the trench portions (at 12, 13, 43), and includes at least one of the cathode region (22) or the collector region (21), wherein an avalanche breakdown voltage of the intermediate region (between 12 and 13/43) is larger than an avalanche breakdown voltage of the diode portion (R2) and smaller than an avalanche breakdown voltage of the transistor portion (R1) (See Fig. 2, Fig. 3) (Notes: the limitation “region” is defined as any of the major subdivisions into which the body or one of its parts is divisible by Merriam-Webster.com). As to claim 25, Gejo discloses further comprising: an intermediate region (between 12 and 13/43) which is arranged between the diode portion (R2) and the transistor portion (R1), is provided with a plurality of the trench portions (at 12, 13, 43), and includes the cathode region (22) and the collector region (21), wherein the intermediate region (between 12 and 13/43) includes a transistor side region (left) in contact with the transistor portion (R1), and the transistor side region (left) includes the trench portion (at 12, 13, 43) having a length (above L2) larger than the first length (above L1) (See Fig. 3) (Notes: the limitation “region” is defined as any of the major subdivisions into which the body or one of its parts is divisible by Merriam-Webster.com). As to claim 26, Gejo further discloses wherein a cathode voltage at which the diode portion (R2) reaches a negative resistance region is smaller than a collector voltage at which the transistor portion (R1) reaches a negative resistance region (See Fig. 2, Fig. 3). As to claim 27, Gejo further discloses wherein an avalanche breakdown voltage in the diode portion (R2) is 0.75 times or more and 0.95 times or less an avalanche breakdown voltage in the transistor portion (R1) (See Fig. 2, Fig. 3). Regarding the recited limitations above, the claim limitations “wherein an avalanche breakdown voltage in the diode portion is 0.7 times or more and less than 1 time an avalanche breakdown voltage in the transistor portion, wherein a cathode voltage at which the diode portion reaches a negative resistance region is equal to or larger than a collector voltage at which the transistor portion reaches a negative resistance region, wherein an avalanche breakdown voltage of the intermediate region is larger than an avalanche breakdown voltage of the diode portion and smaller than an avalanche breakdown voltage of the transistor portion, a cathode voltage at which the diode portion reaches a negative resistance region is smaller than a collector voltage at which the transistor portion reaches a negative resistance region, wherein an avalanche breakdown voltage in the diode portion is 0.75 times or more and 0.95 times or less an avalanche breakdown voltage in the transistor portion” specify an intended use or field of use, and is met by the prior art since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2016/0218101 A1 to Gejo (“Gejo”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2013/0075784 A1 to Ikeda (“Ikeda”). The teaching of Gejo has been discussed above. As to claim 21, although Gejo discloses the diode portion (R2) (See Fig. 2, Fig. 3), Gejo does not further disclose wherein the diode portion includes a lifetime adjustment portion, which adjusts a lifetime of a carrier, on the upper surface side of the semiconductor substrate. However, Ikeda does disclose wherein the diode portion (12) includes a lifetime adjustment portion (127), which adjusts a lifetime of a carrier, on the upper surface side of the semiconductor substrate (See Fig. 1, ¶ 0036). In view of the teaching of Ikeda, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Gejo to have wherein the diode portion includes a lifetime adjustment portion, which adjusts a lifetime of a carrier, on the upper surface side of the semiconductor substrate because a lifetime of a carrier is reduced and diode characteristics (for example, recovery characteristics) can be improved (See ¶ 0036). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached on (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
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Prosecution Timeline

Mar 21, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
45%
Grant Probability
95%
With Interview (+50.1%)
3y 7m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 689 resolved cases by this examiner. Grant probability derived from career allowance rate.

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