DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, and 11-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Basker et al. (US 20180025974 A1) hereinafter referred to as “Basker974”.
Regrading claim 1: Basker974 teaches a method comprising: forming a first interconnect structure (metal lines, para. [0023]; Fig. 3, elements 152-1) including a first portion (see Fig. 3 annotated below) located in a first metal layer (interconnect level, para. [0023]; Fig. 3, element 150) of an interconnect layer of a wafer, the first portion directly laterally separated from other interconnect structures (Fig. 3 annotated below, the elements labeled 152-2 located in the remaining portion) in the first metal layer by dielectric material of the first metal layer (ILD layer, para. [0023]; Fig. 3, element 151); after the forming the first interconnect structure, selectively removing a portion of the dielectric material directly laterally adjacent to the first portion to form an opening (para. [0037]; Fig. 4); forming a dielectric layer on the wafer including on a sidewall of the opening directly laterally adjacent to the first portion (thin conformal insulating layer, para. [0023]; Fig. 8, element 154, the portion of layer 154 that abuts element 152-2 in the first portion); forming conductive material on the wafer (metallic material, para. [0023]; Fig. 8, element 156), the conductive material filling the opening; planarizing the wafer (a CMP process is performed to remove the overburden insulating and metallic material down to the surface of the capping layer, para. [0043], Fig. 8), wherein the planarizing removes the conductive material above the opening to form a remaining portion of the conductive material in the opening, at least a portion of the remaining portion is located in the first metal layer (Fig. 8, para. [0043]); wherein a first electrode (Fig. 3 annotated below, the element 152-2 that is contained within the first portion) of a capacitor includes the first portion and a second electrode of the capacitor (Fig. 8, element 156) includes the remaining portion, a capacitor dielectric of the capacitor (thin conformal insulating layer, Fig. 8, element 154, can be a high-K dielectric material, para. [0044])
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Fig. 3 from Basker974: First portion is indicated by the box with the black dashed outline. Remaining portion is indicated by the box with the red dashed line.
includes a portion of the dielectric layer directly laterally between the first portion and the remaining portion (As claimed the dielectric layer and the capacitor dielectric could be the same material, Fig. 8, the portion of layer 154 that abuts element 152-2 in the first portion is laterally adjacent to the first portion and element 156 in the remaining portion).
Regarding claim 2: Basker974 teaches the selectively removing a portion of the dielectric material exposes a conductive sidewall of the first portion (Fig. 4, the conductive side wall of element 152-2 is exposed).
Regarding claim 3: Basker974 teaches the forming a first interconnect structure (Chose any of the three elements labeled 152-1 in Fig. 1) including a first portion located in a first metal layer includes forming a second interconnect structure (The element labeled 152-2 inside the first portion annotated in Fig. 3 above) including a first portion located in a first metal layer, the first portion of the first interconnect structure and the first portion of the second interconnect structure are directly laterally separated by the dielectric material (ILD layer, Fig. 3, element 151); the opening is directly laterally adjacent to the first portion of the second interconnect structure (See Fig. 7, sidewall of element 152-2 in the first portion); the first electrode includes the first portion of the second interconnect structure (The element labeled 152-2 inside the first portion serves as the first electrode, para. [0044]).
Regarding claim 4: Basker974 teaches after the forming the interconnect structure (Fig. 3, chose any elements labeled 152-1) and prior to the selectively removing, selectively forming a capping layer on the first interconnect structure (“In one embodiment of the invention, after performing the CMP process, a protective layer can be formed on the exposed surfaces of the metal lines 152-1 and 152-2 to protect the metallization from potential damage as a result of subsequent etching processes. For example, for copper metallization, a selective Co deposition process can be performed to selectively deposit a thin capping layer of Co on the exposed surfaces of the metal lines 152-1 and 152-2 shown in Fig. 3. A protective Co capping layer on the metal lines 152-1 and 152-2 would allow for more aggressive etching conditions, etc., when forming air gaps and MIM capacitor structures using techniques discussed hereafter.”, para. [0034]).
Regarding claim 6: Basker974 teaches the selectively removing includes using an etch chemistry to remove the dielectric material, wherein the etch chemistry is selective to material of the capping layer (“dry etch process with an etch chemistry that is selective to the metallic material of the metal lines 152-2 and the dielectric material of the ILD layer 151”, para. [0042], the capping layer is not distinguished from the metallic material of the metal lines here, but it is noted in para. [0034] that the cobalt capping layer allows for more aggressive etching conditions).
Regarding claim 11: Basker974 teaches the forming conductive material on the wafer includes forming a conductive barrier layer on the dielectric layer followed by forming a second type of conductive material on the wafer (“In one embodiment, after forming the damascene openings in the ILD layer 151, a conformal layer of liner material is preferably deposited to line the sidewall and bottom surfaces of the damascene openings in the ILD layer 151 with a thin liner layer (not specifically shown in FIG. 3). The thin liner layer may be formed by conformally depositing one or more thin layers of material such as, for example, tantalum nitride (TaN), cobalt (Co), or ruthenium (Ru), or other liner materials (or combinations of liner materials such as Ta/TaN, TiN, CoWP, NiMoP, NiMoB) which are suitable for the given application. The thin liner layer serves multiple purposes. For example, the thin liner layer serves as a barrier diffusion layer to prevent migration of metallic material (e.g., Cu) into the ILD layer 151. In addition, the thin liner layer serves as an adhesion layer to provide good adhesion to the metallic material (e.g., Cu) that is used to fill the damascene openings in the ILD layer 151 and form the metal lines 152-1 and 152-2 (and vertical vias, not shown).”, para [0034]).
Regarding claim 12: Basker974 teaches the forming the second type of conductive material includes forming a seed layer of the second type of conductive material on the wafer followed by an electroplating process to form a further amount of the second type of conductive material (“The metallization layer 152 is formed by depositing a conductive material such as, for example, copper (Cu), aluminum (Al), or tungsten (W), to fill the damascene openings in the ILD layer 151. The conductive material can be deposited using known techniques such as electroplating, electroless plating, CVD, PVD, or a combination of methods. Prior to filling the damascene openings in the ILD layer 151 with the conductive material, a thin seed layer (e.g., Cu seed layer) may optionally be deposited using a suitable deposition technique such as ALD, CVD or PVD. The seed layer can be formed of a material which enhances adhesion of the metallic material on the underlying material and which serves as catalytic material during a subsequent plating process. For example, a thin conformal Cu seed layer can be deposited over the surface of the substrate using PVD to line the surfaces of the damascene openings, followed by the electroplating of Cu to fill the damascene openings (vias and trenches) formed in the ILD layer 151 and, thus, form a Cu metallization layer 152. The overburden liner, seed, and metallization materials are then removed by performing a chemical mechanical polishing process (CMP) to planarize the surface of the semiconductor structure down to the ILD layer 151, resulting in the intermediate structure shown in FIG. 3”, para. [0035].)
Regarding claim 13: Basker974 teaches after the planarizing the wafer, forming a second interconnect structure (metal lines, Fig. 1, element 162-2) and a third interconnect structure (metal lines , Fig. 2, element 162-3), the second interconnect structure including a first portion in a higher metal layer (Fig. 1, layer 160) to the first metal layer, the second interconnect structure electrically connected to the first interconnect structure, the third interconnect structure including a first portion in the higher metal layer, the third interconnect structure electrically connected to the remaining portion (“metal lines 162-2/162-3, and vertical vias 164/165 to provide wiring and interconnects to the capacitor electrodes of the MIM capacitors formed in the second interconnect level 150 of the BEOL structure 130. Moreover, one or more additional interconnect levels can be formed over the third interconnect level 160, wherein MIM capacitor structures can be integrally formed in any one of the additional interconnect levels using techniques as discussed herein”, para. [0046], Figs. 1 and 2).
Regarding claim 14: Basker974 teaches wherein the forming a first interconnect structure includes planarizing the wafer to define a top surface of the first interconnect structure and a top surface of the portion of the dielectric material directly laterally adjacent to the first portion of the first interconnect structure (“In one embodiment of the invention, after performing the CMP process, a protective layer can be formed on the exposed surfaces of the metal lines 152-1 and 152-2 to protect the metallization from potential damage as a result of subsequent etching processes.”, para. [0036], Fig. 3).
Regarding claim 15: Basker974 teaches wherein the forming a first interconnect structure including a first portion located in a first metal layer includes simultaneously forming a plurality of interconnect structures including portions in the first metal layer (“The metallization layer 152 is formed by depositing a conductive material such as, for example, copper (Cu), aluminum (Al), or tungsten (W), to fill the damascene openings in the ILD layer 151”, para. [0035], Fig. 3), wherein a minimum directly lateral spacing between any two interconnect structures of the plurality of interconnect structures is a first width (width between elements labeled 152-1 in Fig. 3), wherein a closest directly lateral distance between the first portion and the remaining portion is less than the first width (see Fig. 3 annotated above, the separation between the first portion and the remaining portion can be defined to be arbitrarily small or even touching and therefore less than the first width).
Regarding claim 16: Basker974 teaches that the first interconnect structure includes a via structure located directly under the first portion (“It is to be noted that while no vertical vias are shown in the ILD layer 151, it is to be understood that vertical vias would exist in the second interconnect level 150 to provide vertical connections to metallization in the underlying interconnect level 140.”, para [0035])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al. (US 20180025974 A1) hereinafter referred to as “Basker974” in view of Feng et al. (US 20190305077 A1) hereinafter referred to as “Feng077”.
Regarding claim 5: Basker974 teaches that the capping layer (thin capping layer, para. [0036]) is made of cobalt. Basker974 also teaches that electroless plating may be used to deposit a conductive material (“for example, copper (Cu), aluminum (Al), or tungsten (W)”, para. [0035]). However, Basker974 does not explicitly state that the capping layer is deposited by electroless plating.
Feng077 lists cobalt as a material that can be deposited by electroless plating (“For example, the deep trenches 591 may be partially filled with a conductive material (e.g., Co, Ru, etc.) through an electroless deposition process”, para [0051]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to deposit the capping layer with an electroless plating method. This is simply combining prior art elements according to known methods to yield predictable results.
Claim(s) 7-10, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al. (US 20180025974 A1) hereinafter referred to as “Basker974” in view of Chen et al. (US 20210391413 A1) hereinafter referred to as “Chen413”.
Regarding claim 7: Basker974 teaches that the capacitor is a metal-insulator-metal (MIM) capacitor. Basker974 does not explicitly say that the capacitor can function as a decoupling capacitor.
Chen413 teaches that MIM capacitors are used in a wide variety of applications, including as decoupling capacitors (para. [0001]). Therefore, it would have been obvious to a person of ordinary skill in the art to use the MIM capacitor disclosed in Basker974 as a decoupling capacitor. This is simply combining prior art elements according to known methods to yield predictable results.
Regarding claim 8: Basker974 teaches that the capacitor is formed on a substrate or wafer (para. [0019]). Basker974 does not explicitly teach that the wafer is singulated into semiconductor dies or that the first interconnect structure is connected to a first voltage supply rail and that the remaining portion is connected to a second voltage supply rail.
Chen413 teaches that “a package component 100 (which may be a wafer, as illustrated) with multiple device dies 105 defined within. The device dies 105 may all be of the same design and function or may be of different designs and functions.” (para. [0016]). Chen413 also teaches that “decoupling capacitors are also used in power supplies, so that the power supplies may accommodate the variations in current-draw, so that the variation in power supply voltage is minimized” (para. [0002]). Since the first interconnect structure as claimed contains the first electrode and the remaining portion contains the second electrode, it is well known that the two electrodes could be connected to separate voltage rails in order to function as a decoupling capacitor. Furthermore, it is well known to include a MIM capacitor into circuits such as a power-supply circuit in this manner. Additionally, singulating a wafer into a plurality of semiconductor dies is a routine process well known in the semiconductor industry. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the MIM capacitor structure disclosed in Basker974 into a circuit where each electrode is connected to a voltage supply rail for example in a power supply, and to singulate the wafer into multiple semiconductor dies. This is simply combining prior art elements according to known methods to yield predictable results.
Regarding claim 9: Claim 9 is rejected in the same manner as claim 8.
Regarding claim 10: Basker974 teaches that a first semiconductor die includes a capacitor with a first electrode (Fig. 1, elements 152-2) including a portion located in the first metal layer (Fig. 1, element 150) and being a portion of an interconnect structure formed simultaneously with first interconnect structure (damascene process, para. [0033]) the capacitor including a second electrode (Fig. 1, element 156) that includes a portion located in the first metal layer (Fig. 1, element 150) and formed simultaneously with the remaining portion (layer 156 is deposited into both openings in the remaining portion, Fig. 8); a capacitor dielectric (Fig. 1, element 154) including a portion of the dielectric layer (Fig. 1, element 154, as claimed the capacitor dielectric does not have to be a different material than the dielectric layer) located directly laterally between the portion located in the first metal layer and being a portion of an interconnect structure formed simultaneously with first interconnect structure and the portion located in the first metal layer and formed simultaneously with the remaining portion (Fig 1. First interconnect structure 152-1 and second interconnect structure 152-2 are formed by damascene process, para. [0033]). Basker974 does not explicitly teach that the wafer can be singulated into a plurality of identical semiconductor dies.
Chen413 teaches that “a package component 100 (which may be a wafer, as illustrated) with multiple device dies 105 defined within. The device dies 105 may all be of the same design and function or may be of different designs and functions.” (para. [0016]). Singulating a wafer into a plurality of semiconductor dies is a routine process well known in the semiconductor industry. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to singulate the wafer into multiple semiconductor dies. This is simply combining prior art elements according to known methods to yield predictable results.
Regarding claim 17: Basker974 teaches all the limitations of claim 1 as per the rejection above, namely, a method comprising: forming a first interconnect structure including a first portion located in a first metal layer of an interconnect layer of a wafer, the first portion directly laterally separated from other interconnect structures in the first metal layer by dielectric material of the first metal layer; after the forming the first interconnect structure, selectively removing a portion of the dielectric material directly laterally adjacent to the first portion to form an opening; forming a dielectric layer on the wafer including on a sidewall of the opening directly laterally adjacent to the first portion; forming conductive material on the wafer, the conductive material filling the opening; planarizing the wafer, wherein the planarizing removes the conductive material above the opening to form a remaining portion of the conductive material in the opening, at least a portion of the remaining portion is located in the first metal layer; the capacitor includes a first electrode that includes the first portion and a second electrode that includes the remaining portion, a capacitor dielectric of the decoupling capacitor includes a portion of the dielectric layer located directly laterally between the first portion and the remaining portion.
Basker974 does not teach singulating the wafer into a plurality of semiconductor die, or that a first semiconductor die of the plurality of semiconductor die includes a decoupling capacitor. Chen413 teaches singulating the wafer into a plurality of semiconductor die and that the capacitor can function as a decoupling capacitor. Therefore claim 17 is rejected according to the same reasoning used to reject claims 1, 7 and 8.
Regarding claim 18: In addition to the reasoning used to reject claim 17, Basker974 teaches that the selectively removing a portion of the dielectric material exposes a conductive sidewall of the first portion. (Fig. 4, the conductive side wall of element 152-2 is exposed).
Regarding claim 19: In addition to the reasoning used to reject claim 17, the claim language “wherein the first electrode is configured to be biased by a first voltage supply rail and the second electrode is configured to be biased by a second voltage supply rail” is interpreted by the examiner to mean that the first electrode and the second electrode are connected to separate voltage supply rails. Therefore, claim 19 is rejected in the same manner as claim 8.
Regarding claim 20: In addition to the reasoning used to reject claim 17, Basker974 teaches that after the forming the first interconnect structure and prior to the selectively removing, selectively forming a capping layer on the first interconnect structure. (“In one embodiment of the invention, after performing the CMP process, a protective layer can be formed on the exposed surfaces of the metal lines 152-1 and 152-2 to protect the metallization from potential damage as a result of subsequent etching processes. For example, for copper metallization, a selective Co deposition process can be performed to selectively deposit a thin capping layer of Co on the exposed surfaces of the metal lines 152-1 and 152-2 shown in Fig. 3. A protective Co capping layer on the metal lines 152-1 and 152-2 would allow for more aggressive etching conditions, etc., when forming air gaps and MIM capacitor structures using techniques discussed hereafter.”, para. [0034]).
Citation of pertinent prior art
Won et al. (US 20080050874 A1) and Oashi (US 6770930 B2) teach the formation of one capacitor electrode followed by the removal of laterally adjacent dielectric material, then the depositing of a metal layer to form a second capacitor electrode in the same metallization layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)270-0853. The examiner can normally be reached M-F 9:00am-5:00pm.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/ SPE, Art Unit 2898
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