DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 thru 11, 14, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rubin et al. US 10,607,938 B1. Rubin discloses (see, for example, FIG. 1) a microelectronic structure comprising a stack FET array comprising frontside cell T2, backside cell T1, first frontside transistor 122, second frontside transistor 122, and connecting via 134. The first frontside transistor 122 is located horizontally adjacent to the second frontside transistor 122 in the frontside cell T2. The connecting via 134 extends from a frontside of the stacked FET array to a backside of the stacked FET array, wherein the connecting via 134 is located at the boundary of the stacked FET array.
Regarding claims 2-3, see, for example, FIG. 1 wherein Rubin discloses multiple metal
tracks 124/C4/M0/V0/M1/V1, etc. that are associated with the frontside cell T2.
Regarding claims 4, and 14, see, for example, FIG. 1 wherein Rubin discloses multiple frontside metal tracks 124/C4//M0/V0, etc. that are associated with the first frontside transistor 122, and metal tracks 124/C6/M0/V0, etc. that are associated with the second frontside transistor 122.
Regarding claim 5, see, for example, FIG. 1 wherein Rubin discloses a first metal track 114 associated with a backside of the connecting via 134, and a second metal track M3/V2/M2 associated with a frontside of the connecting via 134.
Regarding claims 6, and 11, see, for example, FIG. 1 wherein Rubin discloses the backside cell T1 including a first backside transistor 112 and a second backside transistor 112, wherein the first backside transistor 112 is located horizontally adjacent to the second backside transistor 112.
Regarding claims 7-8, see, for example, FIG. 1 wherein Rubin discloses a plurality of metal tracks includes four metal tracks C1/116/114/102, etc. associated with the backside cell T1.
Regarding claims 9 and 15, see, for example, FIG. 1 wherein Rubin discloses a plurality of metal tracks includes four metal tracks C1/116/114 associated with one backside transistor 112, and metal tracks C2/116/114 associated with the other backside transistor 112.
Regarding claim 10, see, for example, FIG. 1 wherein Rubin discloses a microelectronic structure comprising: a stack FET array, wherein the stack FET array includes a plurality of stacked cells T1/T2, wherein each of the plurality of stacked cells includes a frontside cell T2 and a backside cell T1, wherein each of the frontside cells includes a first frontside transistor 122 and a second frontside transistor 122, wherein the first frontside transistor 122 is located horizontally adjacent to the second frontside transistor 122; and a connecting via 134 extending from a frontside of the stacked FET array to a backside of the stacked FET array, wherein the connecting via 134 is located at a boundary of the stacked FET array.
Claim(s) 1 thru 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. US 2023/0402379 A1. Li discloses (see, for example, FIG. 3M) a microelectronic structure comprising: a stack FET array, wherein the stack FET array includes a frontside cell (transistors 322, paragraph [0068], "a plurality of top epitaxy regions 322") and a backside cell (transistors 320, paragraph [0068], "a plurality of bottom epitaxy regions 320"), wherein the frontside cell and the backside cell are vertically aligned (320, 322), wherein the frontside cell includes a first frontside transistor and a second frontside transistor (right section of FIG. 3M, element 320 between vias 330), wherein the first frontside transistor is located horizontally adjacent to the second frontside transistor; and a connecting via 330 extending from a frontside of the stacked FET array to a backside of the stacked FET array, wherein the connecting via is located at the boundary of the stacked FET array (FIG. 3B element 328, FIG. 3M element 330, paragraph [0072], "via trenches 328 are located between cell boundaries of horizontally adjacent transistors.").
Regarding claims 2-4, Li discloses six frontside metal tracks (FIG. 3D, element 340, 342, paragraph [0076], "signal lines 342 and power lines 340 are formed in the frontside ILD") where each transistor is associated with three metal tracks (FIG. 3M-right section 322 left and right).
Regarding claim 5, Li discloses a via (FIG. 3M, element 330) associated with a frontside (FIG. 3D, element 336 and 342, paragraph [0076], "signal lines 342 and power lines 340 are formed in the frontside ILD") and a backside (FIG. 3M, element 354 and 356) metal track.
Regarding claims 6-9, Li discloses (FIG. 3M-right section) discloses a cell consisting of two back transistors 320 and two frontside transistors 322 adjacent to each other, between vias 330. Each backside transistor 320 is associated with two metal tracks 350, 354.
Regarding claim 10, Li discloses (see, for example, FIG. 3M) a microelectronic structure comprising: a stack FET array, wherein the stack FET array includes a plurality of stacked cells (FIG. 2, elements 102A, 102B, 102C), wherein each of the plurality of stacked cells includes a frontside cell and a backside cell (FIG. 3M-section, element 322 and 320, paragraph [0068], "a plurality of top epitaxy regions 322" and "a plurality of bottom epitaxy regions 320"), wherein each of the frontside cells includes a first frontside transistor and a second frontside transistor, wherein the first frontside transistor is located horizontally adjacent to the second frontside transistor (FIG. 3M-right section, the region 320 between vias 330 shows two frontside transistors next to each other); and a connecting via extending from a frontside of the stacked FET array to a backside of the stacked FET array (FIG. 3M, element 330), wherein the connecting via is located at a boundary of the stacked FET array (FIG. 3B, element 328, FIG. 3M, element 330, paragraph [0072], "via trenches 328 are located between cell boundaries of horizontally adjacent transistors").
Regarding claim 11, Li discloses (see, for example, FIG. 3M-right section) discloses each cell consisting of two back 320 and two frontside transistors 322 adjacent to each other, between vias 330.
Regarding claim 12, Li discloses (see, for example, FIG. 2) an array of three cells 102A
102B, 102C.
Regarding claim 13, Li discloses (see, for example, FIG. 2) an array of three cells 102A, 102B, 102C. A person of ordinary skill in the art would regard it a normal design procedure to repeat this cell to populate the rest of the wafer, and as a result form an array of at least four stacked cells without the exercise of inventive skill.
Regarding claim 14, Li discloses (see, for example, FIG. 3D) for each cell, six frontside metal tracks (element 340, 342, paragraph [0076] "signal lines 342 and power lines 340 are formed in the frontside ILD") where each transistor is associated with three metal tracks (FIG. 3M-right section, element 322 left and right).
Regarding claim 15, Li discloses (see, for example, FIG. 3M) for each cell, two backside metal tracks (FIG. 3M-right section, element 350, 354) associated with each of the backside transistors (FIG. 3M-right section, element 320).
Regarding claim 16, Li discloses (see, for example, FIG. 2, 3M, paragraph [0062], cut X on the left section, and cut Y on the right) a microelectronic structure comprising a first stack FET array (FIG. 2, element 102A), wherein the first stack FET array includes a plurality of first stacked cells, wherein each of the plurality of first stacked cells includes a frontside cell and a backside cell, wherein each of the frontside cells includes a first frontside transistor and a second frontside transistor (paragraph [0059], "Each of the transistor cells 102 includes one or more stacked transistors"), wherein the first frontside transistor is located horizontally adjacent to the second frontside transistor (FIG. 3M-right section 322 and 320, paragraph [0068], "a plurality of top epitaxy regions 322" and "a plurality of bottom epitaxy regions 320"); Li discloses (paragraph [0059]) four stacked transistors per array 102, which corresponds to four frontside and four backside transistors per array. The plurality of cells is defined as two cells with two stacked transistors per cell (two frontside and two backside transistors); a second stack FET array (FIG. 2, element 102B), wherein the second stack FET array includes a plurality of second stacked cells, wherein each of the plurality of second stacked cells includes a frontside cell and a backside cell, wherein each of the backside cells includes a first backside transistor and a second backside transistor (paragraph [0059], "Each of the transistor cells 102 includes one or more stacked transistors"), wherein the first backside transistor is located horizontally adjacent to the second backside transistor (FIG. 3M-right section 322 and 320, paragraph [0068] "a plurality of top epitaxy regions 322" and "a plurality of bottom epitaxy regions 320"); the same rationale for the first array (FIG. 2, element 102A) can be applied to the second array 102B; a connecting via extending from a frontside of the first stack FET array and a frontside of the second stack FET array to a backside of the first stack FET array and a backside of the second stack FET array (FIG. 3M, element 330, paragraph [0073] "interlevel vias 330"), wherein the connecting via is located at an end boundary between the first stack FET array and a beginning boundary of the second stack FET array (FIG. 3M- right section, via 330 is separating two arrays, FIG. 2 element 102A and 102B corresponding to direction Y cross section); a plurality of frontside metal tracks (FIG. 3D, elements 340, 342, paragraph [0076] "signal lines 342 and power lines 340 are formed in the frontside ILD"), wherein two frontside metal tracks of the plurality of frontside metal tracks are associated with each of the frontside transistors 322; and a plurality of backside metal tracks (paragraph [0086], "backside power rails 354"), wherein two backside metal tracks (FIG. 3M-right section element 354) of the plurality of backside metal tracks are associated with each of the backside transistors (FIG. 3M-right section element 320, paragraph [0086] "backside power rails 354").
Regarding claim 17, Li discloses two arrays with the same number of cells (i.e. claim 16). Regarding claim 18-20, Li discloses a third array (FIG. 2, element 102C) with the same number of cells as the first two arrays.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12, 13, and 16 thru 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rubin et al. US 10,607,938 B1 as applied to claims 1-11, 14, and 15 above. Rubin does not expressly disclose the stack FET array including at least three stacked cells or at least four stacked cells. However, it was well known in the art to include multiple stacked cells in a microelectronic structure for utilizing a greater number of cells in the same network according to the preferences of the user. It would have been obvious to one of ordinary skill in the art to have the stack FET array including at least three stacked cells or at least four stacked cells in order to increase device robustness by including a greater number of cells in the same network according the preferences of the user as a matter of obvious design choice, and further since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 13, see the rejection for claim 12 above.
Regarding claim 16, Rubin only discloses a first stack FET array, but does not disclose a second stack FET array; however, it would have been obvious to one of ordinary skill in the art to include another second stack FET array in order to increase robustness of the microelectronic structure while optimizing power efficiency and size as a matter of obvious design choice, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Further, Rubin discloses (see, for example, FIG. 1) a connecting via 134 that lies vertically along the entire microelectronic structure, and plurality of frontside metal tracks M1/V0/M0/C4, and a plurality of backside metal tracks 124/C1/116/114.
Regarding claim 17, it is inherent that the first stack FET array includes a first number of cells, wherein the first number of cells can be the same, less, or greater than a second number of cells of the second stack FET array since these are the only choices (i.e. same, less, or greater) that the first number of cells can be compared in size to a second number of cells of the second stack FET array.
Regarding claim 18, see the rejection for claim 16 above wherein including a third stack FET array would have been an obvious matter of design choice to increase robustness while optimizing power efficiency and size, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 19, it is inherent that the third stack FET array can include a third number of cells, wherein the third number of cells can be the same, less, or greater than a first number of cells of the first stack FET array since these are the only choices (i.e. same, less, or greater) that the third number of cells can be compared in size to a first number of cells of the first stack FET array.
Regarding claim 20, it is inherent that the third stack FET array can include a third number of cells, wherein the third number of cells can be the same, less, or greater than a second number of cells of the second stack FET array since these are the only choices (i.e. same, less, or greater) that the third number of cells can be compared in size to a second number of cells of the second stack FET array.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but the new amendment “stack FET array” is still disclosed by Rubin al. US 10,607,938 B1; further, applicant states Rubin fails to disclose “a stack FET array.” However, as already stated in the rejection above, Rubin discloses a stack FET array that includes a frontside cell T2, backside cell T1, first frontside transistor 122, second frontside transistor 122, and connecting via 134. The FETs in the cells T1 and T2 are stacked on each other and form an array of FETs 122 that extend through the cells T1 and T2, horizontally and vertically. The applicant’s argument filed on 7/28/26 does not provide further rationale why the applicant disagrees with the Examiner regarding Rubin et al. US 10,607,938 B1 except that the applicant disagrees.
Further, the other rejection (i.e. Li et al. US 2023/0402379 A1), which is based on the Written Opinion of the International Searching Authority May 16, 2025 that was disclosed by the applicant’s IDS filed 6/3/25, was not argued or acknowledged in the amendment/argument filed 7/28/26.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
September 13, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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