CTNF 18/611,841 CTNF 90717 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lei(USPGPUB DOCUMENT: 20140273401, hereinafter Lei) in view of Kim (USPGPUB DOCUMENT: 20090117645, hereinafter Kim) . Re claim 1 Lei discloses a semiconductor chip comprising: a substrate(406); an active layer(active portion of 404) on the substrate(406); and at least a portion of the substrate(406) contacts the coated layer. Lei does not disclose a coated layer on side surfaces of the active layer(active portion of 404) and surrounding the side surfaces of the active layer(active portion of 404), wherein an average roughness of the side surfaces of the active layer(active portion of 404) is greater than an average roughness of an upper surface of the active layer(active portion of 404), Kim disclose a coated layer(oxide)[0052 of Kim], wherein an average roughness[0052 of Kim] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Lei in order to increase in the reliability [0006, Kim]. In doing so, a coated layer(oxide)[0052 of Kim] on side surfaces of the active layer(active portion of 404) and surrounding the side surfaces of the active layer(active portion of 404), wherein an average roughness[0052 of Kim] of the side surfaces of the active layer(active portion of 404) is greater than an average roughness of an upper surface of the active layer(active portion of 404)(since 404 of Lei does not disclose an average roughness this may be interpreted as wherein an average roughness[0052 of Kim] of the side surfaces of the active layer(active portion of 404) is greater than an average roughness of an upper surface of the active layer(active portion of 404)), Re claim 2 Lei and Kim disclose the semiconductor chip of claim 1, wherein the coated layer is a conformal layer on the side surfaces of the active layer(active portion of 404). Re claim 3 Lei and Kim disclose the semiconductor chip of claim 1, wherein a horizontal width of the active layer(active portion of 404) decreases away from the substrate(406). Re claim 4 Lei and Kim disclose the semiconductor chip of claim 1, wherein the side surfaces of the active layer(active portion of 404) comprise at least one crack. Re claim 5 Lei and Kim disclose the semiconductor chip of claim 4, wherein the coated layer fills the crack of the active layer(active portion of 404). Re claim 6 Lei and Kim disclose the semiconductor chip of claim 1, wherein a first region of the upper surface of the substrate(406) is in contact with the active layer(active portion of 404), a second region of the upper surface of the substrate(406) is in contact with the coated layer, and an average roughness of the first region of the upper surface of the substrate(406) is less than an average roughness of the second region of the upper surface of the substrate(406). Re claim 7 Lei and Kim disclose the semiconductor chip of claim 6, wherein the substrate(406) comprises at least one crack in the upper surface thereof, and the crack is in the second region of the upper surface of the substrate(406). Re claim 8 Lei and Kim disclose the semiconductor chip of claim 7, wherein the coated layer fills the crack of the substrate(406). Re claim 9 Lei and Kim disclose the semiconductor chip of claim 1, wherein an area of a lower surface of the active layer(active portion of 404) is less than an area of the upper surface of the substrate(406). Re claim 10 Lei and Kim disclose the semiconductor chip of claim 1, wherein the side surfaces of the active layer(active portion of 404) covered by the coated layer, are not exposed to an outside, and the upper surface of the active layer(active portion of 404) is exposed to an outside. Re claim 11 Lei discloses a semiconductor chip comprising: a substrate(406); a plurality of active layer(active portion of 404)s on the substrate(406) and apart from each other in a horizontal direction; wherein a horizontal width of each of the plurality of active layer(active portion of 404)s decreases away from the substrate(406). Lei does not disclose a coated layer in contact with side surfaces of the plurality of active layer(active portion of 404)s and an upper surface of the substrate(406), Kim disclose a coated layer(oxide)[0052 of Kim] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Lei in order to increase in the reliability [0006, Kim]. In doing so, a coated layer(oxide)[0052 of Kim] in contact with side surfaces of the plurality of active layer(active portion of 404)s and an upper surface of the substrate(406), Re claim 12 Lei and Kim disclose the semiconductor chip of claim 11, wherein the plurality of active layer(active portion of 404)s comprise a first active layer(active portion of 404) and a second active layer(active portion of 404), a first side surface of the first active layer(active portion of 404) and a second side surface of the second active layer(active portion of 404) face each other, the first side surface and the second side surface comprise sidewalls of a division line, a portion of the upper surface of the substrate(406) comprises a bottom of the division line, and the coated layer is a conformal layer on the sidewalls and the bottom of the division line. Re claim 13 Lei and Kim disclose the semiconductor chip of claim 12, wherein an average roughness of each of the sidewalls and the bottom of the division line is greater than an average roughness of the upper surface of the plurality of active layer(active portion of 404)s. Re claim 14 Lei and Kim disclose the semiconductor chip of claim 12, further comprising: a plurality of cracks in the sidewalls and the bottom of the division line, wherein the coated layer fills the plurality of cracks on the sidewalls and the bottom of the division line. Re claim 15 Lei and Kim disclose the semiconductor chip of claim 12, wherein a distance between the sidewalls comprising the division line decreases toward the substrate(406), and the bottom of the division line has a rounded shape. Re claim 16 Lei discloses in Fig 4A-4D a manufacturing method of a semiconductor chip, the manufacturing method comprising: forming a protection layer(402) on an active layer(active portion of 404) of a substrate(406); removing a portion(see Fig 4B) of the protection layer(402) and a portion of the active layer(active portion of 404) along a partition due line inside the active layer(active portion of 404); and removing the protection layer(402) on the active layer(active portion of 404). Lei does not disclose forming a coated layer in a space where the portion of the protection layer(402) and the portion of the active layer(active portion of 404) are removed; Kim disclose forming a coated layer(oxide)[0052 of Kim] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Lei in order to increase in the reliability [0006, Kim]. In doing so, forming a coated layer(oxide)[0052 of Kim] in a space where the portion of the protection layer(402) and the portion of the active layer(active portion of 404) are removed; Re claim 17 Lei and Kim disclose the manufacturing method of claim 16, wherein the removing includes removing the portion of the protection layer(402) and the portion of the active layer(active portion of 404) using a laser ablation process. Re claim 18 Lei and Kim disclose the manufacturing method of claim 16, wherein the forming the coated layer(oxide)[0052 of Kim] includes forming the coated layer(oxide)[0052 of Kim] by applying a coating solution into the space using a spray method. Re claim 19 Lei and Kim disclose the manufacturing method of claim 16, wherein the forming the coated layer(oxide)[0052 of Kim] includes forming the coated layer(oxide)[0052 of Kim] by applying a coating solution into the space using a brush method. Re claim 20 Lei and Kim disclose the manufacturing method of claim 16, further comprising: after the forming of the coated layer(oxide)[0052 of Kim], curing the coated layer(oxide)[0052 of Kim] by irradiating heat or light on the coated layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812 Application/Control Number: 18/611,841 Page 2 Art Unit: 2812 Application/Control Number: 18/611,841 Page 3 Art Unit: 2812 Application/Control Number: 18/611,841 Page 4 Art Unit: 2812 Application/Control Number: 18/611,841 Page 5 Art Unit: 2812 Application/Control Number: 18/611,841 Page 6 Art Unit: 2812 Application/Control Number: 18/611,841 Page 7 Art Unit: 2812
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