DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group I and Species 1, corresponding to claims 1, 2, and 4-7, in the reply filed on 7/31/26 is acknowledged. The traversal is on the ground(s) that there is no serious burden and the explanation was not satisfactory. This is not found persuasive because the restriction gave an explanation. To further detail, the burden is very clearly seen and shown in the figures and detailed in the specification by figure 6 shows the heat dissipation covers completely covers the sidewall and figure 7 shows the heat dissipation covers only partially covers the sidewall.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, and 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Molla et al., US 10,741,446.
Regarding claim 1, Molla (figure 3 & marked up figure 3 below) teaches a method of manufacturing chip structure comprising:
attaching a wafer 312 onto a first carrier 332, the wafer 312 includes a plurality of dies 342;
dicing the wafer 312 to singulate the plurality of dies along a dicing lane 322 which is located on the active surface of each of the plurality of dies and located between the adjacent dies, a groove 322 is formed between the adjacent singulated dies 342, and a lateral surface of each of the plurality of singulated dies 342 is visible from the groove;
forming a plurality of heat dissipation covers 352 on the plurality of singulated dies 342 to constitute a plurality of chip structures 342/352, each of the plurality of heat dissipation covers 352 is directly formed on the back surface and the lateral surface of one of the plurality of singulated dies 342 to cover the back surface and the lateral surface, wherein each of the plurality of heat dissipation covers 352 includes a first portion 1, a second portion 2 and a connection portion 3 which is located between and connected to the first 1 and second 2 portions, the first portion 1 is formed on the back surface, the second portion 2 is formed on the lateral surface via the groove, the connection portion 3 is formed on an outer corner of the back surface, there is a first space 4 between the connection portions 3 of the adjacent heat dissipation covers 352 and a second space 5 between the second portions 2 of the adjacent heat dissipation covers 352, the first space 4 is less than the second space 5, and the first 4 and second 5 spaces become smaller gradually from the second carrier to an opening of the groove, a first exposed surface of the first portion 1 is connected to a third exposed surface of the connection portion 3, a second exposed surface of the second portion 2 is connected to a fourth exposed surface of the connection portion 3, the first portion 1 has a first thickness in a direction perpendicular to the back surface, the second portion 2 has a second thickness in a direction parallel to the back surface, the first thickness ( of 1) is greater than the second thickness ( of 2), the second thickness (of 2) is reduced gradually from the connection portion 3 to the active surface such that the second exposed surface of the second portion 2 extends toward the second carrier obliquely.
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Molla fails to teach a back surface of each of the plurality of dies is attached on the first carrier and an active surface of each of the plurality of dies is exposed when attached to the first carrier; attaching the diced wafer onto a second carrier, the active surface of each of the plurality of singulated dies is attached on the second carrier; and removing the first carrier to expose the groove, the back surface and the lateral surface of each of the plurality of singulated dies.
Camacho (figures 3b-4c) teaches a back surface 128 of each of the plurality of dies 124 is attached on the first carrier and an active surface 130 of each of the plurality of dies 124 is exposed when attached to the first carrier (figure3b); singulating the wafer (figure 3c); attaching the diced wafer onto a second carrier 136 (figure 4c), the active surface 130 of each of the plurality of singulated dies 124 is attached on the second carrier 136; and removing the first carrier to expose the groove, the back surface and the lateral surface of each of the plurality of singulated dies.
Though Camacho fails to specifically teach the first carrier, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a first carrier in the invention of Camacho because a skilled artisan knows that a first carrier is used, the wafer is not left unsupported during processing because that leads to damage, and it is the most efficient way to transport the dies to the second carrier of figures 4b-c. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
With respect to claim 2, Molla (see marked up figure 3) above teaches the second portion 2 and the connection portion 3 are located both sides of a first imaginary line which extends along the back surface, the first 1 and second 2 portions are located both sides of a second imaginary line which extends along the lateral surface, the second exposed surface has an area larger than that of the lateral surface.
As to claim 4, Molla (see marked up figure 3 above) teaches a first connection face of the connection portion 3 is located on a first imaginary line (horizontal portion of 3) which extends along the back surface, a second connection face (vertical portion of 3) of the connection portion 3 is located on a second imaginary line which extends along the lateral surface, the second connection face has an area larger than that of the first connection face.
In re claim 5, Molla (see marked up figure 3 above) teaches the connection portion 3 has a third thickness in the direction parallel to the back surface, the third thickness is greater than the second thickness of the second portion 2 and is reduced gradually from the connection portion 3 to the second portion 2, the fourth exposed surface of the connection portion 3 extends toward the second carrier obliquely.
Concerning claim 6, though Molla fails to teach a width of the groove is greater than or equal to 10 µm, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the width through routine experimentation (MPEP 2144.05).
Pertaining to claim 7, though Molla fails to teach the first thickness of the first portion is greater than or equal to 0.5 µm, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the thickness through routine experimentation (MPEP 2144.05).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/ Primary Examiner, Art Unit 2891 8/20/26
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