DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 7-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20230420460 A1).
Regarding claim 1, Huang et al. teaches a microelectronic structure comprising:
a stacked FET that includes a frontside source/drain (105d) and a backside source/drain (105b) [Fig. 1A, ¶0003]; and
a connection via (118b) that passes through the backside source/drain (105b), wherein the connection via (118b) extends from a frontside surface of the backside source/drain to a backside surface of the backside source/drain, wherein the backside source/drain surrounds the connection via as it passes through the backside source/drain [Fig. 1A, ¶0045].
Regarding claim 2, Huang et al. teaches the microelectronic structure of claim 1, further comprising:
a backside connection (as seen in attached Fig. 1A) located on the backside surface of the backside source/drain (105b), wherein the backside connection extends laterally across the backside surface of the backside source/drain [Fig. 1A, ¶¶0051, 0056].
PNG
media_image1.png
525
422
media_image1.png
Greyscale
Regarding claim 3, Huang et al. teaches the microelectronic structure of claim 2, wherein the backside connection (as seen in attached Fig. 1A) is connected to the connection via (118b) [Fig. 1A, ¶0030].
Regarding claim 4, Huang et al. teaches the microelectronic structure of claim 3, further comprising: a frontside contact (149) connected to the frontside source/drain [Fig. 1A, ¶0051].
Regarding claim 5, Huang et al. teaches the microelectronic structure of claim 4, wherein the frontside contact (149) is independent of the connection via (118b) [Fig. 1A, ¶0051].
Regarding claim 7, Huang et al. teaches the microelectronic structure of claim 4, wherein the frontside contact (149) extends laterally to connect with the connection via (118b) [Fig. 1A, ¶0051].
Regarding claim 8, Huang et al. teaches the microelectronic structure of claim 7, wherein the backside connection (as seen in attached Fig. 1A), the connection via (118b), and the frontside contact (149) form a shared contact, wherein the shared contact is in contact with a frontside surface of the frontside source/drain, wherein portions of a sidewall of the shared contact are in contact with the backside source/drain, and wherein the shared contact is in contact with a backside surface of the backside source/drain [Fig. 1a, ¶0051].
Regarding claim 9, Huang et al. teaches a microelectronic structure comprising:
a stacked FET that includes a first frontside source/drain (105d), a second frontside source/drain (105c), a first backside source/drain (105b), and a second backside source/drain (105a);
a first wiring scheme (118b and 149) is utilized to make connections to the first frontside source/drain and the first backside source/drain; and
a second wiring scheme (118a and 122) is utilized to make connections to the second frontside source/drain and the second backside source/drain, wherein the first wiring scheme and the second wiring scheme are different wiring schemes;
wherein the first wiring scheme comprises;
a first connection via (118b) that passes through the first backside source/drain (105b), wherein the first connection via extends from a frontside surface of the first backside source/drain to a backside surface of the first backside source/drain, wherein the first backside source/drain surrounds the first connection via as it passes through the first backside source/drain [Fig. 1A, ¶0051].
Regarding claim 10, Huang et al. teaches the microelectronic structure of claim 9, wherein the first wiring scheme further comprises:
a first backside connection (as seen in attached Fig. 1A) located on the backside surface of the first backside source/drain (105b), wherein the first backside connection extends laterally across the backside surface of the first backside source/drain [Fig. 1A, ¶0051].
Regarding claim 11, Huang et al. teaches the microelectronic structure of claim 10, wherein the first backside connection (as seen in attached Fig. 1A) is connected to the first connection via (118b) [Fig. 1A, ¶0051].
Regarding claim 12, Huang et al. teaches the microelectronic structure of claim 11, further comprising:
a first frontside contact (149) connected to the first frontside source/drain (105d) [Fig. 1A, ¶0051].
Regarding claim 13, Huang et al. teaches the microelectronic structure of claim 12, wherein the first frontside contact (149) is independent of the connection via (118b) [Fig. 1A, ¶0051].
Regarding claim 14, Huang et al. teaches the microelectronic structure of claim 13, wherein the second wiring scheme comprises:
a second connection via (118a) that passes through the second backside source/drain (105a), wherein the second connection via extends from a frontside surface of the second backside source/drain to a backside surface of the second backside source/drain, wherein the second backside source/drain surrounds the second connection via as it passes through the second backside source/drain [as seen in attached Fig. 1A, ¶0045].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20230420460 A1) in view of Hwang et al. (US 20240047463 A1).
Regarding claim 6, Huang et al. teaches the microelectronic structure of claim 5.
Huang et al. doesn’t teach a frontside interlayer dielectric layer.
Hwang et al. teaches a frontside interlayer dielectric layer (140) located between the connection via (TV2) and the frontside contact (UCA2) [Fig. 5, ¶0036].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the microelectronic structure as taught by Huang et al. with the inclusion of a frontside interlayer dielectric layer as taught by Hwang et al. because it would ensure the most efficient pathway and minimal interference.
Regarding claim 15, Huang et al. teaches the microelectronic structure of claim 14, wherein the second wiring scheme further comprises:
Huang et al. doesn’t teach a second backside connection.
Hwang et al. teaches a semiconductor device including a multi-bridge channel field effect transistor that has a second backside connection (UCA2) located on the backside surface of the second backside source/drain, wherein the second backside connection extends laterally across the backside surface of the second backside source/drain [as seen in attached Fig. 5, ¶0104].
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the stacked transistor device as taught by Huang et al. with the teachings of a second backside connection as taught by Hwang et al. because it would allow for a further integrated device that would have less interference and greater efficiency.
PNG
media_image2.png
510
496
media_image2.png
Greyscale
Regarding claim 16, Huang et al. in view of Hwang et al. teaches the microelectronic structure of claim 15, further comprising:
a second frontside contact (UCA2) connected to the second frontside source/drain (USD2) [Fig. 5, ¶0106].
Regarding claim 17, Huang et al. in view of Hwang et al. teaches the microelectronic structure of claim 16, wherein the second frontside contact (UCA2) extends laterally to connect with the second connection via (USD2) [Fig. 5, ¶0106].
Regarding claim 18, Huang et al. in view of Hwang et al. teaches the microelectronic structure of claim 17, wherein the second backside connection (BCA2), the second connection via (TV2), and the second frontside contact (UCA2) form a shared contact (in combination with Huang et al. it would be a shared contact as both first and second wiring schemes are connected as such), wherein the shared contact is in contact with a frontside surface of the second frontside source/drain (105c), wherein portions of a sidewall of the shared contact (118a and 150a) are in contact with the second backside source/drain, and wherein the shared contact is in contact with a backside surface of the second backside source/drain [Fig. 1a, ¶0051, Huang et al. Fig. 5, ¶0106, Hwang et al.].
Regarding claim 19, Huang et al. in view of Hwang et al. teaches the microelectronic structure of claim 18, further comprising:
a first backside cap (120b) located on the backside surface of the first backside connection (as seen in attached Fig. 1A); and
a second backside cap (120a) located on the backside surface of the second backside connection (as seen in attached Fig. 1A) [Fig. 1A, ¶0085, Huang et al.].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20230420460 A1) in view of Huang et al. '659 (US 20220165659 A1).
Regarding claim 20, Huang et al. teaches a microelectronic structure comprising:
a stacked FET that includes a first frontside source/drain (105d), a second frontside source/drain (105c), a first backside source/drain (105b), and a second backside source/drain (105a);
a first wiring scheme (118b and 149) is utilized to make connections to the first frontside source/drain and the first backside source/drain;
a second wiring scheme (as seen in attached Fig. 1A) is utilized to make connections to the second frontside source/drain (105c) and the second backside source/drain (105a), wherein the first wiring scheme and the second wiring scheme are different wiring schemes (as seen in attached Fig. 1A);
wherein the first wiring scheme comprises;
a connection via (118b) that passes through the first backside source/drain (105b), wherein the connection via extends from a frontside surface of the first backside source/drain to a backside surface of the first backside source/drain (as seen in attached Fig. 1A), wherein the first backside source/drain surrounds the connection via as it passes through the first backside source/drain (as seen in attached Fig. 1A);
a backside connection (as seen in attached Fig. 1A) located on the backside surface of the first backside source/drain, wherein the backside connection extends laterally across the backside surface of the first backside source/drain; and
a backside cap (120b) located on the backside surface of the backside connection; wherein the second wiring scheme comprises;
a backside contact (as seen in attached Fig. 1A) in contact with a backside side surface of the second backside source/drain (105a).
Huang et al. doesn’t teach a backside power distribution network.
Huang et al. ‘659 teaches a backside power distribution network is connected to the backside contact [Fig. 14, ¶0040, power rails are seen to be synonymous].
It would have been obvious for a person with ordinary skill in the art before the effective filing date to combine the microelectronic structure as taught by Huang et al. with the backside power distribution network as taught by Huang et al. ‘659 because it would allow for the structure to have a stable power supply and efficient voltage delivery.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOR MOHAMMAD ISMAIL TAHIR whose telephone number is (571)272-6166. The examiner can normally be reached Monday Friday, 8 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NOOR MOHAMMAD ISMAIL TAHIR/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights