The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election of the embodiment of figure 1 in the reply filed on 07/06/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 and 5-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the elected embodiment of figure 1 for the claimed limitation of “circuits formed on the respective insulating layers and including either wiring with a plating layer formed on a surface thereof or wiring with no plating layer formed thereon”, as recited in claim 1, because all the circuits include wiring with a plating layer formed on a surface thereof.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5, 8, 10, 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “plating layer”, as recited in claims 3, 5, 8, 10, 11-12 is unclear because the element “plating layer” is not necessarily present in the claimed device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-14 are rejected under 35 U.S.C. 103 as being unpatentable over Buynoski (6,246,118).Regarding claim 1, Buynoski teaches in figure 3 and related text a multilayer substrate comprising:
a plurality of insulating layers 11 in which a cutline area (arbitrarily chosen) is defined;
circuits (the metal structures) formed on the respective insulating layers 11 and including either wiring METAL3 with a plating layer formed on a surface thereof or wiring with no plating layer formed thereon;
vias VIA 1-4 formed in at least one of the insulating layers; and
lead wiring (one of the METAL lines) formed on one of the insulating layers where circuits connected to one another via the vias are formed, the lead wiring extending to the cutline area.
Buynoski does not explicitly state using insulating layers.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use insulating layers Buynoski’s device, in order to have better control over the location of the wiring layers.
Regarding the claimed limitations of insulating layers, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
The formation of insulating layers does not produce a structure which is different from a structure which is formed using only one insulating layer.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding claim 2, Buynoski does not teach that a thickness of the wiring is between 40 μm and 200 μm, or a spacing between the circuits is 2 μm and 8 μm if the circuits include both the wiring and the plating layer formed on the surface of the wiring, or is 10 μm and 30 μm if the circuits include the wiring with no plating layer formed thereon.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a thickness of the wiring is between 40 μm and 200 μm, or a spacing between the circuits is 2 μm and 8 μm if the circuits include both the wiring and the plating layer formed on the surface of the wiring, or is 10 μm and 30 μm if the circuits include the wiring with no plating layer formed thereon in Buynoski’s device, in order to optimize the device characteristics.
Regarding claim 3, Buynoski teaches in figure 3 and related text the wiring is formed on the surface of the wiring that is electrically connected to the lead wiring via the vias.
Regarding claim 5, Buynoski teaches in figure 3 and related text the circuits formed on the same layer as the lead wiring includes both the wiring.
Regarding claim 6, Buynoski teaches in figure 3 and related text the lead wiring is formed with the same level as or a lower level than the wiring.
Regarding claim 7, Buynoski does not teach in figure 3 and related text if the lead wiring is formed at a lower level than the wiring, the lead wiring is formed with the same level as a seed layer formed between the corresponding insulating layer and the wiring.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use if the lead wiring is formed at a lower level than the wiring, the lead wiring is formed with the same level as a seed layer formed between the corresponding insulating layer and the wiring in Buynoski’s device, in order to improve the device characteristics.
Regarding claim 8, Buynoski teaches in figure 3 and related text a plating layer is not formed on a surface of the lead wiring.
Regarding claim 9, Buynoski teaches in figure 4 and related text a lead wiring protective layer 40A formed on the lead wiring.
Regarding claim 10, Buynoski teaches in figure 3 and related text the lead wiring protective layer 40A is removed after the formation of the plating layer on the wiring or remains when the insulating layers are stacked on the circuits.
Regarding claim 11, Buynoski teaches in figure 3 and related text that the lead wiring protective layer is formed with the same level as the wiring or as a combined height of the wiring and the plating layer.
Regarding claim 12, Buynoski teaches in figure 3 and related text that the lead wiring is formed with the same level as the wiring that is formed at the same layer as the lead wiring, and the lead wiring protective layer is formed with the same level as the plating layer.
Regarding claim 13, Buynoski teaches in figure 3 and related text that the insulating layer 11 where the lead wiring is formed protrudes outwardly beyond the cutline area (chosen as such), and the lead wiring is formed on the corresponding insulating layer to extend outwardly beyond the cutline area.
Regarding claim 14, Buynoski teaches in figure 3 and related text an electronic device comprising: the multilayer substrate of any one of claim 1; and a semiconductor device (part of the semiconductor structure of Buynoski) electrically connected to the multilayer substrate, wherein the electronic device operates under the control of the semiconductor device or uses an electromagnetic force provided by the circuits formed on the multilayer substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
7/16/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights