DETAILED ACTION
This Office Action is in response to Amendment filed September 8, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
On lines 23 and 27, “electrodes, of the” should be replaced with “electrodes of the”.
On lines 24 and 28, “electrodes, that are” should be replaced with “electrodes that are”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsuno et al. (US 12,394,718)
Regarding claims 1 and 3, Matsuno et al. disclose a memory device (Fig. 19A) comprising: a first cell array stack (stack to the left and underneath wavy truncated lines) including a plurality of first gate electrodes (46) (col. 25, lines 48-51) spaced apart from each other in a first direction (vertical direction), and a first channel structure (portion, structure or one of 601 and 602) (col. 14, lines 61-62 and col. 17, lines 11-12) passing through the plurality of first gate electrodes, wherein, for each of the plurality of first gate electrodes (46) below an uppermost first gate electrode, an end of the first gate electrode is vertically non-overlapping with a first gate electrode immediately above the first gate electrode; a second cell array stack (stack to the right and over wavy truncated lines) disposed on the first cell array stack, wherein the second cell array stack includes a plurality of second gate electrodes (46) spaced apart from each other in the first direction and a second channel structure (another portion, another structure or another of 601 and 602) passing through the plurality of second gate electrodes, wherein, for each of the plurality of second gate electrodes (46) below an uppermost second gate electrode, an end of the second gate electrode is vertically non-overlapping with a second gate electrode immediately above the second gate electrode, and wherein the plurality of second gate electrodes (46) overlap the plurality of first gate electrodes in the first direction (vertical direction); and a vertical contact (76A and/or 76B) (col. 25, lines 63-67) extending in the first direction and passing through: one of the plurality of first gate electrodes (46), lower first gate electrodes (46), of the plurality of first gate electrodes, that are arranged below the one of the plurality of first gate electrodes, one of the plurality of second gate electrodes (46), and lower second gate electrodes (46), of the plurality of second gate electrodes, that are arranged below the one of the plurality of second gate electrodes (claim 1), further comprising: a plurality of first insulating patterns (inner, middle and outer patterns of 74) (col. 25, line 36) arranged between the vertical contact (76A and/or 76B) and the lower first gate electrodes (46) to electrically separate the vertical contact from the lower first gate electrodes, because (a) Applicants do not specifically claim what the “patterns” refer to, (b) the insulating trench spacer 74 would have three patterns or portions along the thickness direction since (i) the insulating trench spacer 74 is in contact with the conductive liner 76A and the electrically conductive layer 46, and (ii) atoms constituting the conductive liner 76A and the electrically conductive layer 46 should inherently diffuse into the insulating trench spacer 74 to a certain degree as otherwise the insulating trench spacer 74 and the conductive liner 76A/electrically conductive layer 46 would not be firmly bonded to each other, and (c) therefore, the inner, middle and outer portions or patterns of the insulating trench spacer 74 would have different material compositions, albeit a small difference, among themselves; and a plurality of second insulating patterns (inner, middle and outer patterns of 74) arranged between the vertical contact and the lower second gate electrodes (46) to electrically separate the vertical contact from the plurality of lower second gate electrodes, see the explanations on the term “patterns” above (claim 3).
Allowable Subject Matter
Claims 2 and 4-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sung et al. (US 12,757,720)
Otsu (US 2023/0013984)
Shimomura et al. (US 12,279,425)
Hopkins et al. (US 2021/0358805)
Choi et al. (US 12,278,201)
Applicants' amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 October 7, 2026
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