DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 10/23/2025. Claims 1-18 and 20-21 are pending and are under examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-10, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Randhawa et al. (USP 5,341,048) in view of Park (US 2008/0265964).
Regarding claims 1, 7 and 12, Randhawa et al.’s figure 3 shows a device comprising a converting circuit (I2, T2, T3) configured to transform a single-ended input signal (CLK) into differential output signals (C1, C2) and including a transmission gate (T2) configured to output one of the differential output signals (C1); and a first routing circuit (T4) (i) configured to route the single-ended input signal as the other of the differential output signals (C2) of the converting circuit, and (ii) having a shorter signal propagation delay than the converting circuit (T4 is shorter path than I2 to T2 or I2 to T3).
Randhawa et al. reference does not show a buffering circuit configured to amplify the differential output signals (C1 and C2) as called for in claims 1, 7, 12.
Park’s 4 shows a device comprising a converting circuit (10) configured to transform a single-ended input signal (sig_in) into differential output signals (N2, N3) further including a buffering circuit (20) configured to amplify the differential output signals to provide a complementary output signals; and a second device (INV 12, INV13) couple to receive the complementary output signals. The buffer circuit is to correct the duty cycle of the differential output signals (paragraph 0049). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Park’s buffering circuit in Randhawa et al.’s circuit arrangement of the purpose of correcting the duty cycle of the differential output signals as taught by Park reference.
Regarding claims 2, 8 and 13, the first routing circuit include a buffer (T4).
Regarding claims 3, 9 and 14, the first routing circuit include a transistor (T4) in a source following structure.
Regarding claim 10, wherein the transforming is such that the single-ended input signal traverses through an inverter (I2) and the transmission gate (T2).
Claim(s) 1-4, 7-14, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2008/0265964) in view of Randhawa et al. (USP 5,341,048).
Regarding claims 1, 7 and 12, Park’s figure 4 shows a device comprising a converting circuit (Inv7, Inv9, buf3) configured to transform a single-ended input signal (sig_in) into differential output signals (N2, N3) and including a buffer (buf3) configured to output one of the differential output signals (N3); and a first routing circuit (buf2) (i) configured to route the single-ended input signal as the other of the differential output signals (N2) of the converting circuit, and (ii) having a shorter signal propagation delay than the converting circuit (Buf2 is shorter path than Inv7, Inv9 or Inv7 and buf3); a buffering circuit (20) configured to amplify the differential output signals to provide a complementary output signals; and a second device (INV 12, INV13) couple to receive the complementary output signals.
The difference seen between Park and the present invention is that Park uses buf3 instead of a transmission gate as called for in claims 1, 7 and 12.
Randhawa et al.’s figure 1B shows a device comprising a converting circuit (I1, 3, 4) configured to transform a single-ended input signal (sig_in) into differential output signals (C1, C2) and including a transmission gate (3) configured to output one of the differential output signals. Park’s buffer circuit (Buf3) functions as a transmission gate in which is the input signal at the node N1 is transmitted to the output signal node N3. Thus, one skilled in the art would have been recognized that Park’s buffer circuit (buf3) and Randhawa et al.’s transmission gate (3) are functional equivalent. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Park’s buf3 replaced by Randhawa et al.’s transmission gate because they are functional equivalent and a substitution of one for the other would not alter the circuit operation.
Regarding claims 2, 8 and 13, the first routing circuit include a buffer (buf2).
Regarding claims 3, 9 and 14, the first routing circuit include a transistor (N5, N6) in a source following structure.
Regarding claims 4 and 20, a first inverter (Inv7 of Park) ; the transmission gate (3 of the combined references) between the first inverter and the buffering circuit (20); and a second inverter (Inv9) between the first inverter and the buffering circuit, wherein the first routing circuit (buf2) is between an input of the first inverter and an output of the second inverter.
Regarding claim 10, the combination of Park and Randhawa reference shows the transforming is such that the single-ended input signal would be traversed through an inverter (Inv7) and the transmission gate (3).
Regarding claim 11, the transforming is such the single-ended input signal traverses through a pair of inverters (Inv7 and Inv9).
Allowable Subject Matter
Claims 5-6, 15-18 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2842 1/15/2026
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