DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 21 Mar 2024 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4–6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 refers to “the plurality of grooves” in line 2. There is insufficient antecedent basis for this limitation in the claim because neither claim 4 nor claim 1 has previously introduced “a plurality of grooves”. The examiner suggests the following amendment:
4. The semiconductor device according to claim 1, wherein the semiconductor chip includes a plurality of grooves in the outer peripheral area.
Regarding claim 5, the examiner finds the language “each of another grooves except for the groove that is arranged at the position closest to the predetermined area” in lines 5–7 to be somewhat confusing. First, the phrase “each of another grooves” is an awkward construction that would make more sense as either “each of the other grooves of the plurality of grooves” or “every other groove of the plurality of grooves”. Second, it seems redundant to state “except for the groove that is arranged at the position closest to the predetermined area” at the end of the claim since the rest of the claim has already stated that this ‘closest’ groove is the one being compared to, and of course the closest groove will not have a larger width or depth in comparison to itself. The examiner suggests the following amendment to improve clarity:
5. The semiconductor device according to claim 4, wherein[[,]] the groove that is arranged at a position closest to the predetermined area from among the plurality of grooves is constituted such that at least one of a width and a depth is larger than that of every other groove of the plurality of grooves .
Claim 6 refers to “the width and the depth” in line 3. There is insufficient antecedent basis for this limitation in the claim because neither claim 6 nor claim 4, upon which claim 6 depends, has previously introduced “a width and a depth”. The problem could be resolved by simply changing this portion of claim 6 to “a width and a depth”. Alternatively, the problem could be resolved by having claim 6 depend on claim 5 (instead of on claim 4), since claim 5 already introduced “a width and a depth”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1–3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Japanese published patent application JP-2009032244-A by Sasaki (relying on attached machine translation).
Regarding claim 1, Sasaki teaches:
A semiconductor device 1-6 (FIG. 12, “semiconductor device 1-6 of the sixth embodiment” ¶[0073], which differs from the first embodiment 1-1 of FIG. 1 in that in FIG. 12 “a stepped portion A is continuously provided around the entire circumference of the semiconductor chip 5” ¶[0073]) comprising:
a wiring substrate 3 (“support substrate 3” ¶[0017]);
a semiconductor chip 5 that is mounted on the wiring substrate 3 (“a semiconductor chip 5 mounted face-down on a support substrate 3” ¶[0017]); and
a sealing resin 9 that is filled in a gap between the wiring substrate 3 and the semiconductor chip 5 (“The support substrate 3 and the semiconductor chip 5 are sandwiched together … and the area between them is filled with resin 9” ¶[0017]) and that extends to an upper surface A of the semiconductor chip 5 (as shown in the top view of FIG. 12 and in the cross-sectional view of FIG. 1), wherein
the semiconductor chip 5 includes a groove A (“This stepped portion A is shaped by cutting out the peripheral edge of the back surface 5b of the semiconductor chip 5” ¶[0021], wherein the stepped portion A is formed in FIG. 2(2) as a “wide groove 21c” ¶[0028]) that is formed in an outer peripheral area A (“a stepped portion A is continuously provided around the entire circumference of the semiconductor chip 5” ¶[0073]) located around a circumference (as shown in FIG. 12) of a predetermined area 5b (“the back surface 5b of the semiconductor chip 5” ¶[0021]) disposed on the upper surface of the semiconductor chip 5, the outer peripheral area A including a peripheral edge of the upper surface 5b of the semiconductor chip 5, and that captures an extending portion of the sealing resin 9 (“the resin 9 that spills out from between the support substrate 3 and the semiconductor chip 5 and climbs up the side wall of the semiconductor chip 5 is accumulated in the stepped portion A, preventing it from riding up to the top of the back surface 5b of the semiconductor chip 5” ¶[0035]).
PNG
media_image1.png
358
435
media_image1.png
Greyscale
PNG
media_image2.png
342
490
media_image2.png
Greyscale
PNG
media_image3.png
741
479
media_image3.png
Greyscale
Note that independent claim 1 could be differentiated from the prior art of Sasaki by amending claim 1 to point out features of the groove of the present application that are not found in Sasaki. For example, Sasaki’s groove A (FIGS. 12 and 1) has only one vertical sidewall because the entire bottom of the groove A is a “stepped portion A” located around a circumference of the predetermined area 5b of the upper surface of the semiconductor chip 5. In contrast, every groove 124 in the present application is defined by two vertical sidewalls.
Regarding claim 2, Sasaki teaches:
The semiconductor device 1-6 (FIG. 12) according to claim 1, wherein the groove A is formed at a position, included in the outer peripheral area A located on the upper surface of the semiconductor chip 5, along at least a side that constitutes the peripheral edge of the upper surface of the semiconductor chip 5 (as shown in FIG. 12, “a stepped portion A is continuously provided around the entire circumference of the semiconductor chip 5” ¶[0073]; the stepped portion A is formed in FIG. 2(2) as a “wide groove 21c” ¶[0028] in the upper surface of the semiconductor chip 5).
Regarding claim 3, Sasaki teaches:
The semiconductor device 1-6 (FIG. 12) according to claim 1, wherein, at the extending portion that extends to the upper surface of the semiconductor chip 5, the sealing resin 3 upheaves to a position that is higher than the upper surface of the semiconductor chip 5 and covers the outer peripheral area A located on the upper surface of the semiconductor chip 5 (““the resin 9 that spills out from between the support substrate 3 and the semiconductor chip 5 and climbs up the side wall of the semiconductor chip 5 is accumulated in the stepped portion A, preventing it from riding up to the top of the back surface 5b of the semiconductor chip 5” ¶[0035]).
Explanation: the “sixth embodiment” of the semiconductor device 1-6 of FIG. 12 differs from the “first embodiment” of the semiconductor device 1-1 of FIG. 1 in that in FIG. 12 “a stepped portion A is continuously provided around the entire circumference of the semiconductor chip 5” ¶[0073], whereas in FIG. 1 the stepped portion A is only located along two sides of the semiconductor chip 5. Since FIG. 12 provides only a top view and not a cross-sectional view of the semiconductor device 1-6, we may rely on the related embodiment of the semiconductor device 1-1 of FIG. 1 for a cross-sectional view of features shared in common by both semiconductor devices 1-1 and 1-6. FIG. 1 shows an extending portion of the sealing resin 3 that extends to a portion of the upper surface of the semiconductor chip 5. That is, as shown in both FIGS. 1 and 12, the semiconductor chip 5 has two upper surfaces: (1) the highest horizontal surface 5b of the semiconductor chip 5 (which is analogous to the present application’s “predetermined area” that is not to be covered by the sealing resin 3), and (2) the horizontal surface of the stepped portion A (which is analogous both to the present application’s “outer peripheral area located around a circumference of a predetermined area” and to the present application’s “groove” since the stepped portion A is formed in FIG. 2(2) as a “wide groove 21c” ¶[0028]). Since both FIGS. 1 and 12 show that an extending portion of the sealing resin 3 extends to the horizontal surface of the stepped portion A, it is a true statement that an extending portion of the sealing resin 3 extends onto a portion of the upper surface of the semiconductor chip 5.
(A difference between FIGS. 1 and 12 is that in the embodiment of FIG. 12, both the groove A and the extending portion of the sealing resin 3 on the upper surface of the semiconductor chip 5 completely surround, in a top view, the predetermined area 5b, whereas in FIG. 1 the groove A is located only on the left and right sides of the semiconductor chip, and the extending portion of the sealing resin 3 is located only on the right side of an upper surface the semiconductor chip 5.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Japanese published patent application JP-2012138394-A by Fujishima (relying on attached machine translation).
Regarding claim 7, Sasaki teaches the semiconductor device 1-6 (FIG. 12) according to claim 1, as shown above. However, Sasaki fails to teach:
“wherein an area in which the sealing resin 9 is applied is located in the outer peripheral area A of the semiconductor chip 5.”
Sasaki’s FIG. 3(2) shows and paragraphs [0032, 0033, 0035] explain that the sealing resin 9 is applied by the nozzle 31 directly to the wiring substrate 3 at a location outside and near to the peripheral edge of the semiconductor chip 5, but not directly above the outer peripheral area A of the semiconductor chip 5, as required by claim 7 of the present application and as shown in FIG. 3 of the present application.
PNG
media_image4.png
714
481
media_image4.png
Greyscale
In the same field of endeavor, Fujishima shows in FIG. 12(b) that an area in which a sealing resin 16 (“first encapsulation resin material 16”) is applied is located in an outer peripheral area of a semiconductor chip 12a (“memory chip 12a”).
PNG
media_image5.png
713
464
media_image5.png
Greyscale
Fujishima explains in ¶[0062]: “As shown in Figure 12, while supplying the first sealing resin material 16 to one side of the outer periphery of the chip stack 11, the dispenser 32, which serves as a supply means for supplying the first sealing resin material 16, is moved from the outer periphery of the chip stack 11 toward the center of the chip stack 11. This allows the first sealing resin material 16 to ride up smoothly onto the outer periphery of the memory chip 12a, thereby forming a good ride-up portion 16a. Therefore, in this embodiment as well, similar to the first embodiment, it is possible to prevent the bump electrodes of the interface chip 12b from being covered by the first sealing resin material 16.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Sasaki’s semiconductor device 1-6 (FIG. 12) could be formed by moving the nozzle 31 for the sealing resin 9 to be located above the outer peripheral area A of the semiconductor chip 5 (instead of locating the nozzle 31 near to and outside of the peripheral edge of the semiconductor chip 5 as shown in Sasaki’s FIG. 3(2)) so as to apply the sealing resin 9 in the outer peripheral area of the semiconductor chip 5. It would have been obvious to move Sasaki’s nozzle 31 in FIG. 3(2) from outside the peripheral edge of the semiconductor chip 5 to above the outer peripheral area A of the semiconductor chip 5 while applying the sealing resin 9 because Fujishima’s FIG. 12 shows a dispenser 32 being moved from outside of the peripheral edge of a semiconductor chip 12a to above an outer peripheral area of the upper surface of the semiconductor chip 12a while applying the sealing resin 16. Both Sasaki’s resin application in FIG. 3 and Fujishima’s resin application in FIG. 12 accomplish a similar result of applying a sealing resin both as un underfill between a semiconductor chip and a wiring substrate while simultaneously applying an extending portion of the sealing resin to at least an outer peripheral area of the semiconductor chip. It would be reasonable to expect that in combination with Fujishima’s resin application method, Sasaki’s stepped portion A would continue to function as a groove to capture the extending portion of the sealing resin 9, thereby preventing the sealing resin 9 from reaching the predetermined area 5b of the upper surface of the semiconductor chip 5.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The closest prior art of Sasaki, as cited above in reference to claims 1–3, fails to teach that
“the semiconductor chip includes the [a] plurality of grooves in the outer peripheral area.”
Sasaki’s FIG. 12 only shows a single groove A in the outer peripheral area A. In another reference, patent application publication US 2021/0020531 A1 by Cetegen et al. (“Cetegen” hereafter) shows in FIG. 2B that it is a known method to use a sequence of parallel notches (i.e., the spaces between the flow control features 230) to slow, but not completely stop, the flow of a sealing resin 210 (“underfill 210”) in a flow direction perpendicular to the flow control features 230. See ¶[0034]: “Referring now to FIG. 2B, the flow of an underfill 210 across a package substrate 205 with a flow control feature 230 that comprises lines that are orthogonal to the direction of flow (as indicated by the arrow) is shown, in accordance with an embodiment. As shown, the leading edge 218 of the underfill 210 has advanced a distance X2 at time t1. X2 is less than X1 and indicates that the flow rate has been slowed by the flow control feature 230. The flow rate of the underfill 210 is decreased because a pinching point is formed at the edge of each of the lines that the underfill passes over.” However, unlike in the present application, Cetegen only teaches the use of a plurality of grooves to slow the flow of an underfill in the direction perpendicular to the grooves (and to speed up the flow of an underfill in the direction parallel to the grooves). Cetegen makes use of parallel grooves that are either perpendicular to or parallel to the flow direction of the underfill in order to slow down or speed up the progress of the underfill in different areas of a package substrate to avoid the formation of voids in the underfill beneath the die. In other words, Cetegen’s goal was to modify the rates of flow of the underfill across the substrate in various regions (such as between adjacent dies, outside die edges, or underneath a die) in order to “even out” the flow rate in the various regions so that the underfill can completely fill the gap between the substrate and a die without forming a void underneath a die. As such, Cetegen does not teach the use of a plurality of grooves to completely stop the flow of the underfill so as to prevent a predetermined area from being covered by the underfill.
PNG
media_image6.png
435
429
media_image6.png
Greyscale
Thus, it would not be obvious to replace Sasaki’s single groove A (FIG. 12) with Cetegen’s plurality of grooves (the spaces between the flow control features 230 in FIG. 2B) because Cetegen does not specifically teach that the sealing resin is blocked from passing a last one of the plurality of grooves so as to not have any sealing resin in a predetermined area beyond the last one of the plurality of grooves. (Note also that all of Cetegen’s examples of flow control features are located on the substrate, not on the top surface of a chip mounted on the substrate as in the present application.)
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 5 would be allowable at least for the reason that, as explained above, the closest prior art of Sasaki and Cetegen does not teach a plurality of grooves as required by claim 4, upon which claim 5 depends. Also, Cetegen’s plurality of grooves (the spaces between the flow control features 230 in FIG. 2B) appear to have uniform widths and depths. Thus, Cetegen fails to teach that:
“the groove that is arranged at a position closest to the predetermined area from among the plurality of grooves is constituted such that at least one of a width and a depth is larger than that of each of another grooves except for the groove that is arranged at the position closest to the predetermined area.”
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 6 would be allowable at least for the reason that, as explained above, the closest prior art of Sasaki and Cetegen does not teach a plurality of grooves as required by claim 4, upon which claim 6 depends. Also, Cetegen’s plurality of grooves (the spaces between the flow control features 230 in FIG. 2B) appear to have uniform widths and depths. Thus, Cetegen fails to teach that:
“the plurality of grooves are constituted such that at least one of the width and the depth is larger as the groove is located closer to the predetermined area from among the plurality of grooves.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0343803 A1—FIG. 3 shows a first groove 23D for damming the flow of a first resin 23, and a second groove 25D for damming the flow of a second resin 25 (but does not show the use of multiple grooves for stopping a single resin); the second resin 25 has an extending portion (relevant to claim 1) that extends onto an outer peripheral area of the upper surface of the semiconductor chip 12 (but the semiconductor chip 12 does not include any groove on its upper surface for stopping the flow of the second resin 25).
US 2019/0267287 A1—FIG. 20 shows a plurality of grooves/notches 110 in the sidewalls (but not on the upper surface) of the semiconductor chips 42 and 70 not to impede flow of the encapsulant 68, but rather to improve adhesion between the encapsulant 68 and the sidewalls of the semiconductor chips 42 and 70.
JP-2010251625-A—FIGS. 9, 10C, and 10D show the application of an underfill resin 5 which also covers the side surface 9 and an outer peripheral area of the upper surface 8 of a semiconductor chip 1, relevant to claim 1 (but there is no groove on the upper surface 8 of the semiconductor chip 1)
JP-H11345834-A (from the IDS)—FIG. 2(a) shows the application of a sealing resin 8 to an outer peripheral area 1a of a semiconductor chip 1, relevant to claim 7.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.J.M./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights