DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (KR10-2023-0145526 Republic of Korea 10/27/2023).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 03/21/2024, 08/26/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 03/21/2024. These drawings are review and accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Li et al (US 11,069,385 B1 hereinafter “Li”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Li, for example in Figs. 1-8, discloses a semiconductor memory device (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), comprising:
a first chip (e.g., chip 14/16; in Figs 4, 6 related in Figs. 1-3, 5, 7-8) including a first array matrix (e.g., array-1; in Fig. 4 related in Figs. 1-3, 5-8) and a second array matrix adjacent to each other (e.g., array-2; in Fig. 4 related in Figs. 1-3, 5-8), the first array matrix and the second array matrix each including a plurality of memory cells (e.g., 20a; in Fig. 4 related in Figs. 1-3, 5-8); and
a second chip below the first chip (e.g., chip 12; in Figs. 4, 6 related in Figs. 1-3, 5, 7-8), the second chip including a plurality of sense amplifiers (e.g., SA-E and SA-O; in Figs. 4, 6 related in Figs. 1-3, 5, 7-8) configured to drive the memory cells of the first array matrix and the second array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), wherein a plurality of first cell bit lines are in the first array matrix (e.g., DL0 and DL1; in Figs. 4-6 related in Figs. 1-3 related in Figs. 7-8), and a plurality of second cell bit lines are in the second array matrix (e.g., DL0 and DL1; in Figs. 4-6 related in Figs. 1-3, 7-8), wherein a plurality of first bit lines and a plurality of first complementary bit lines (e.g., DL0, DL1 and DL0*, DL1*; in Figs. 4-6 related in Figs. 1-3, 7-8) are below the first array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), and a plurality of second bit lines and a plurality of second complementary bit lines are below the second array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein each of the first bit lines is connected to one of the first cell bit lines (e.g., line 88 is connected to cell bit lines; in Figs. 2, 4-6 related in Figs. 1, 3, 7-8), each of the first complementary bit lines is connected to one of the second cell bit lines (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), each of the second bit lines is connected to one of the second cell bit lines (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), and each of the second complementary bit lines is connected to one of the first cell bit lines (see for example in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein the sense amplifiers comprise a plurality of first sense amplifiers of which at least a portion is below the first array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8) and a plurality of second sense amplifiers of which at least a portion is below the second array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein a pair of one of the first bit lines and a corresponding one of the first complementary bit lines are connected to a corresponding one of the first sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), and
wherein a pair of one of the second bit lines and a corresponding one of the second complementary bit lines are connected to a corresponding one of the second sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8).
Regarding claim 2, Li, for example in Figs. 1-8, discloses wherein: the first cell bit lines respectively connected to the first bit lines and the first cell bit lines respectively connected to the second complementary bit lines alternate with each other (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above); and the second cell bit lines respectively connected to the first complementary bit lines and the second cell bit lines respectively connected to the second bit lines alternate with each other (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above).
Regarding claim 3, Li, for example in Figs. 1-8, discloses wherein a connection of the first bit line and the first cell bit line, a connection of the second complementary bit line and the first cell bit line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above), a connection of the first complementary bit line and the second cell bit line, and a connection of the second bit line and the second cell bit line are in a boundary region between the first array matrix and the second array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above).
Regarding claim 4, Li, for example in Figs. 1-8, discloses wherein each of the first bit line, the first complementary bit line, the second bit line and the second complementary bit lines is in the first chip, and includes a plurality of upper wires and a plurality of upper vias (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above).
Regarding claim 5, Li, for example in Figs. 1-8, discloses wherein the second chip comprises a plurality of lower wires and a plurality of lower vias that connect the first bit line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above), the first complementary bit line, the second bit line, and the second complementary bit line to the sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 12-15, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 11,069,385 B1 hereinafter “Li”) in view of Lee et al (US 2022/0358993 A1 hereinafter “Lee”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 6, Li, for example in Figs. 1-8, discloses the claimed invention as discussed above. However, Li is silent with regard to an upper/lower bonding pad.
In the same field of endeavor, Lee, for example in Figs. 1-15, discloses an upper/lower bonding pad (see for example in Figs. 4-5 related in Figs. 1-3, 6-15).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Li such as integrated assemblies comprising folded-digit-line-configurations (see for example in Figs. 1-8 of Li) by incorporating the teaching of Lee such as memory circuit, memory structures, and method for fabricating a memory device (see for example in Figs. 1-15 of Lee). In order to provide for high density storage devices, a three dimensional (3D) stacked memory stack structure can be formed by vertically stacking multiple memory cells (see Lee disclosed).
Regarding claim 12, the above Li/Lee, combination discloses wherein: the second chip includes a plurality of lower bonding pads, a plurality of first connection layers, and a plurality of second connection layers that connect the first bit lines and the first complementary bit lines to the sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Lee, as discussed above); and one of the first connection layers is connected to a first input terminal of a corresponding one of the sense amplifiers, and one of the second connection layers corresponding to the one of the first connection layers is connected to a second input terminal of the corresponding one of the sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Lee, as discussed above); and each of the first connection layers is connected to one of the lower bonding pads; and each of the second connection layers is connected to another one of the lower bonding pads (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Lee, as discussed above).
Regarding claim 13, the above Li/Lee, combination discloses wherein the one of the lower bonding pads is connected to the first bit line, and the another one of the lower bonding pads is connected to the first complementary bit line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Lee, as discussed above).
Regarding claim 14, the above Li/Lee, combination discloses wherein a group of the plurality of lower bonding pads corresponds to both one of the first connection layers and a corresponding one of the second connection layers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Lee, as discussed above).
Regarding claim 15, the above Li/Lee, combination discloses wherein half of the group of the lower bonding pads are connected to the first bit line, a remaining half of the group of the lower bonding pads are connected to the first complementary bit line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Lee, as discussed above).
Regarding Independent Claim 19, Li, for example in Figs. 1-8, discloses a semiconductor memory device (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), comprising:
a first chip (e.g., chip 14/16; in Figs 4, 6 related in Figs. 1-3, 5, 7-8) including an array matrix, the array matrix (e.g., arrays; in Fig. 4 related in Figs. 1-3, 5-8) including a plurality of memory cells (e.g., 20a/20b; in Fig. 4 related in Figs. 1-3, 5-8); and
a second chip (e.g., chip 12; in Figs. 4, 6 related in Figs. 1-3, 5, 7-8) comprising a plurality of sense amplifiers (e.g., SA-E and SA-O; in Figs. 4, 6 related in Figs. 1-3, 5, 7-8), the sense amplifiers being below the first chip and configured to drive memory cells of the array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein a plurality of cell bit lines are in the array matrix (e.g., DL0, DL1 and DL0*, DL1*; in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein a plurality of bit lines and a plurality of complementary bit lines are below the array matrix (e.g., lines 88 is connected to cell bit lines; in Figs. 2-6 related in Figs. 1, 7-8),
wherein a pair of one of the bit lines and a corresponding one of the complementary bit lines are connected to a corresponding one of the sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein the second chip includes, a plurality of first connection layers, and a plurality of second connection layers that connect the bit lines and the complementary bit lines to the sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above),
wherein one of the first connection layers is connected to a first input terminal of a corresponding one of the sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above), and a corresponding one of the second connection layers is connected to a second input terminal of the corresponding one of the sense amplifiers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above),
wherein each of the first connection layers is connected to a corresponding one of bonding pads, and wherein each of the second connection layers is connected to a corresponding one of the bonding pads (see for example in Figs. 4-6 related in Figs. 1-3, 7-8, as discussed above).
However, Li is silent with regard to a plurality of lower bonding pads.
In the same field of endeavor, Lee, for example in Figs. 1-15, discloses a plurality of lower bonding pads (see for example in Figs. 4-5 related in Figs. 1-3, 6-15).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Li such as integrated assemblies comprising folded-digit-line-configurations (see for example in Figs. 1-8 of Li) by incorporating the teaching of Lee such as memory circuit, memory structures, and method for fabricating a memory device (see for example in Figs. 1-15 of Lee). In order to provide for high density storage devices, a three dimensional (3D) stacked memory stack structure can be formed by vertically stacking multiple memory cells (see Lee disclosed).
Regarding claim 20, the above Li/Lee, combination discloses wherein a group of the lower bonding pads is corresponds to both one of the first connection layers, and a corresponding one of the second connection layers (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Lee, as discussed above).
Claims 7-11, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US 11,069,385 B1 hereinafter “Li”) in view of IIDA (US 2013/0250646 A1 hereinafter “Iida”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 7, Li, for example in Figs. 1-8, discloses the claimed invention as discussed above. However, Li is silent with regard to shield line.
In the same field of endeavor, Iida, for example in Figs. 1-15, discloses shield line (e.g., GDL0, /GDL0 operation as the shield wires between the main bit lines MBL0 and /MBL0; in Figs 4-5 related in Figs. 1-3, 6-15).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Li such as integrated assemblies comprising folded-digit-line-configurations (see for example in Figs. 1-8 of Li) by incorporating the teaching of Lee such as semiconductor memory device (see for example in Figs. 1-15 of Iida). In order to achieve the objective, in the present disclosure, a main memory array is divided into two sub-memory arrays, and the number of sub bit lines is twice the number of main bit lines, thereby enlarging the pitches of the main bit lines to twice the pitches of the sub bit lines (see Iida, paragraph [0014]).
Regarding claim 8, the above Li/Iida, combination discloses wherein, among one of the first bit lines and a corresponding one of the first complementary bit lines that are commonly connected to a corresponding one of the first sense amplifiers, one is straight line, and the other one is a refracted line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Iida, as discussed above).
Regarding claim 9, the above Li/Iida, combination discloses wherein the refracted line crosses and is insulated from the shield line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Iida, as discussed above).
Regarding claim 10, the above Li/Iida, combination discloses wherein the refracted line comprises a first portion and a second portion positioned at both sides of the shield line, a connection portion crossing and insulated from the shield line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Iida, as discussed above), a first via connecting between the first portion and the connection portion, and a second via connecting between the second portion and the connection portion (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Iida, as discussed above).
Regarding claim 11, the above Li/Iida, combination discloses wherein the refracted line crosses and is insulated from at least one among the first bit lines and the first complementary bit lines (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Iida, as discussed above).
Regarding Independent Claim 16, Li, for example in Figs. 1-8, discloses a semiconductor memory device (see for example in Figs. 4-6 related in Figs. 1-3, 7-8), comprising:
a first chip (e.g., chip 14/16; in Figs 4, 6 related in Figs. 1-3, 5, 7-8) comprising an array matrix (e.g., arrays; in Fig. 4 related in Figs. 1-3, 5-8), the array matrix including a plurality of memory cells (e.g., 20a/20b; in Fig. 4 related in Figs. 1-3, 5-8); and
a second chip (e.g., chip 12; in Figs. 4, 6 related in Figs. 1-3, 5, 7-8) comprising a plurality of sense amplifiers (e.g., SA-E and SA-O; in Figs. 4, 6 related in Figs. 1-3, 5, 7-8), the sense amplifiers being below the first chip and configured to drive memory cells of the array matrix (see for example in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein a plurality of cell bit lines are in the array matrix (e.g., DL0, DL1 and DL0*, DL1*; in Figs. 4-6 related in Figs. 1-3, 7-8),
wherein a plurality of bit lines and a plurality of complementary bit lines are below the array matrix (e.g., lines 88 is connected to cell bit lines; in Figs. 2-6 related in Figs. 1, 7-8),
wherein a pair of one of the bit lines and a corresponding one of the complementary bit lines are connected to a corresponding one of the sense amplifiers (at least one of a shield line), and
wherein a second one of the bit lines, or a second one of the complementary bit lines is between a pair of one of the bit lines and a corresponding one of the complementary bit lines commonly connected to a corresponding one of the sense amplifiers (at least one of a shield line).
However, Li is silent with regard to at least one of a shield line.
In the same field of endeavor, Iida, for example in Figs. 1-15, discloses at least one of a shield line (e.g., GDL0, /GDL0 operation as the shield wires between the main bit lines MBL0 and /MBL0; in Figs 4-5 related in Figs. 1-3, 6-15).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Li such as integrated assemblies comprising folded-digit-line-configurations (see for example in Figs. 1-8 of Li) by incorporating the teaching of Lee such as semiconductor memory device (see for example in Figs. 1-15 of Iida). In order to achieve the objective, in the present disclosure, a main memory array is divided into two sub-memory arrays, and the number of sub bit lines is twice the number of main bit lines, thereby enlarging the pitches of the main bit lines to twice the pitches of the sub bit lines (see Iida, paragraph [0014]).
Regarding claim 17, the above Li/Iida, for example in Figs. 1-15, discloses wherein among one of the bit lines and a corresponding one of the complementary bit lines commonly connected to a corresponding one of the sense amplifiers, one is straight line, and the other one is a refracted line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Iida, as discussed above).
Regarding claim 18, the above Li/Iida, combination discloses wherein the refracted line crosses and is insulated from the shield line (see for example in Figs. 4-6 related in Figs. 1-3, 7-8 of Li and also see in Figs. 4-5 related in Figs. 1-3, 6-15 of Iida, as discussed above).
Conclusion
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/THA-O H BUI/ Primary Examiner, Art Unit 2825 06/08/2026
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