DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 7, 8, 11, 13 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Andrys (Fig. 5); 11,888,452].
Regarding claim 1, Andrys discloses an amplifier network comprising a two-state circuit (110) which is configured to be coupled to the circuit terminal (the input terminal receiving the input signal RF_in) and a voltage source (VDD) and a reference potential (ground) and wherein the two-state circuit (110) including a first node (the node between the elements M1 and R2) selectively (SW5) couplable to the reference potential (ground), and a series-diode protection circuit (109) configured to be coupled to the circuit terminal (the input terminal receiving the input signal RF_in) and the reference potential (ground) and the first node (the node between the elements M1 and R2) of the two-state circuit (110).
Regarding claims 2 and 8, wherein the two-state circuit (110) selectively (SW5) couples the first node (the node between the elements M1 and R2) to the reference potential (ground) when a large voltage signal (RF_in) is present on the circuit terminal (the input terminal receiving the input signal RF_in), and otherwise (when the switch SW5 is opened) couples the first node (the node between the elements M1 and R2) to the voltage source (VDD).
Regarding claims 5 and 11, Andrys further comprising a capacitor (C2) coupled to the first node (the node between the elements M1 and R2) and configured to be coupled to the reference potential (ground).
Regarding claim 7, Andrys discloses an amplifier network comprising an input terminal (the input terminal receiving the input signal RF_in), an output terminal (the terminal producing the output signal RF_out), a voltage source terminal (the terminal applying the VDD voltage source) configured to be coupled to a voltage source (VDD), a two-state circuit (110) coupled to the input terminal (the input terminal receiving the input signal RF_in) and the voltage source terminal (the terminal applying the VDD voltage source) and a reference potential (ground) and wherein the two-state circuit (110) including a first node (the node between the elements M1 and R2) selectively (SW5) couplable to the reference potential (ground), and a series-diode protection circuit (109) coupled to the input terminal (the input terminal receiving the input signal RF_in) and the reference potential (ground) and first node (the node between the elements M1 and R2) of the two-state circuit (110).
Regarding claim 13, Andrys further comprising a self-biased switch (SW6) coupled between the input terminal (the input terminal receiving the input signal RF_in) and the reference potential (ground).
Regarding claim 14, wherein the circuit (100) is a low noise amplifier and the output signal (RF_out) is an amplified version of the input signal (RF_in).
Allowable Subject Matter
Claims 3, 4, 6, 9, 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claims 15-20 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
2023/0308059 teaches an amplifier circuit with the amplifier protection circuit.
2020/0220503 also teaches an amplifier circuit with the amplifier protection circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached MONDAY-FRIDAY 5AM-11:00PM.
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/HENRY CHOE/ Primary Examiner, Art Unit 2843
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