Prosecution Insights
Last updated: July 17, 2026
Application No. 18/612,576

METHOD AND SYSTEM OF GENERATING A COMPILER-AWARE NEURAL NETWORK MODEL

Non-Final OA §101§103
Filed
Mar 21, 2024
Examiner
WAESCO, JOSEPH M
Art Unit
Tech Center
Assignee
MediaTek Singapore Pte. Ltd.
OA Round
1 (Non-Final)
47%
Grant Probability
Moderate
1-2
OA Rounds
11m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 47% of resolved cases
47%
Career Allowance Rate
218 granted / 462 resolved
-12.8% vs TC avg
Strong +42% interview lift
Without
With
+42.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
42 currently pending
Career history
516
Total Applications
across all art units

Statute-Specific Performance

§101
30.4%
-9.6% vs TC avg
§103
67.9%
+27.9% vs TC avg
§102
1.3%
-38.7% vs TC avg
§112
0.2%
-39.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 462 resolved cases

Office Action

§101 §103
DETAILED ACTION Claims 1-20 are pending. Claims 1-20 are considered in this Office action. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/21/2024 has been acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The initialed and dated copy of Applicant’s IDS form 1449 is attached to the instant Office action. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Alice – Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claims 1 and 11 recite the limitations for obtaining compilation optimization information of a compilation of a neural network model, the compilation optimization information indicating one or more modifications to the neural network model during the compilation of the neural network model, and the one or more modifications being based on hardware information of a target hardware that the neural network model is to be deployed onto (Receiving Information, an Observation, a Mental Process; Fundamental Economic Process, a Certain Method of Organizing Human Activity), modifying the neural network model based on the one or more modifications indicated by the compilation optimization information (Analyzing the Information, an Evaluation, a Mental Process; Fundamental Economic Process, a Certain Method of Organizing Human Activity), compiling the modified neural network model into a compiled neural network model (Analyzing the Information, an Evaluation, a Mental Process; Fundamental Economic Process, a Certain Method of Organizing Human Activity), and deploying the compiled neural network model onto the target hardware (Transmitting the Analyzed Information, an Evaluation and judgment, a Mental Process; Fundamental Economic Process, a Certain Method of Organizing Human Activity), which under their broadest reasonable interpretation, covers performance of the limitation in the mind for the purposes of a Fundamental Economic Process, but for the recitation of generic computer components. That is, other than reciting a system and processing circuitry, nothing in the claim element precludes the step from practically being performed or read into the mind for the purposes of a Fundamental Economic Process, a Certain Method of Organizing Human Activity. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas, an observation, evaluation, and judgment. Further, as described above, the claims recite limitations for a Fundamental Economic process, a “Certain Method of Organizing Human Activity”. Accordingly, the claim recites an abstract idea. This judicial exception is not integrated into a practical application. In particular, the claim recites the above stated additional elements to perform the abstract limitations as above. The system, and processing circuitry are recited at a high-level of generality (i.e., as a generic software/module performing a generic computer function of storing, retrieving, sending, and processing data) such that they amount to no more than mere instructions to apply the exception using generic computer components. Even if taken as an additional element, the receiving and transmitting steps above are at best insignificant extra-solution activity as these are receiving, storing, and transmitting data as per the MPEP 2106.05(d). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, when considered both individually and as an ordered combination. As discussed above with respect to integration of the abstract idea into a practical application, the additional element being used to perform the abstract limitations stated above amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. The claim is not patent eligible. Applicant’s Specification states: “[0114] FIG. 11 shows a flowchart outlining a process 1100 according to embodiments of the disclosure. The process 1100 can be executed by processing circuitry (e.g., CPU, GPU, APU, TPU, or the like) of an apparatus such as a computer system 1200 in FIG. 12.” Which shows that these steps can be performed on any generic computing device like a CPU, GPU, etc. which can be used to perform the abstract limitations, such as a laptop, phone, desktop, etc., and from this interpretation, one would reasonably deduce the aforementioned steps are all functions that can be done on generic components, and thus application of an abstract idea on a generic computer, as per the Alice decision and not requiring further analysis under Berkheimer, but for edification the Applicant’s specification has been used as above satisfying any such requirement. This is “Applying It” by utilizing current technologies. For the receiving and transmitting steps that were considered extra-solution activity in Step 2A above, if they were to be considered additional elements, they have been re-evaluated in Step 2B and determined to be well-understood, routine, conventional, activity in the field. The background does not provide any indication that the additional elements, such as the computer, various means, etc., nor the receiving and transmitting steps as above, are anything other than a generic, and the MPEP Section 2106.05(d) indicates that mere collection or receipt, storing, or transmission of data is a well‐understood, routine, and conventional function when it is claimed in a merely generic manner (as it is here). For these reasons, there is no inventive concept. The claim is not patent eligible. Claims 2-10 and 12-20 contain the identified abstract ideas, further narrowing them, with the no new additional elements to be considered as part of a practical application or under prong 2 of the Alice analysis of the MPEP, thus not integrated into a practical application, nor are they significantly more for the same reasons and rationale as above. Examiner notes Claims 1-10 recite no additional elements. After considering all claim elements, both individually and in combination, Examiner has determined that the claims are directed to the above abstract ideas and do not amount to significantly more. Therefore, the claims and dependent claims are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. See Alice Corporation Pty. Ltd. v. CLS Bank International, No. 13–298. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-6, 8-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (U.S. Publication No. 2025/025,9388) in view of Shen (U.S. Publication No. 2022/018,0125). Regarding Claims 1 and 11, Lin, a system and method for using one or more neural networks to generate three-dimensional (3D) models, teaches a method for constructing a neural network, the method comprising: modifying the neural network model based on the one or more modifications indicated by the compilation optimization information ([0144] the machine learning models are modified and optimized based the received information) compiling the modified neural network model into a compiled neural network model ([0144] compiled/optimized neural network which has been modified); and deploying the compiled neural network model onto the target hardware ([0144] deploying neural network model which is optimized) Although Lin teaches obtaining compilation optimization information of a compilation of a neural network model, the compilation optimization information indicating one or more modifications to the neural network model during the compilation of the neural network model, and the one or more modifications being based on information of a target that the neural network model is to be deployed onto ([0141-144] there is a host of information which is used for modifications to neural networks, both training and retraining), it does not explicitly state a target hardware. Shen teaches a hardware target as in [0035] along with training, retraining, and optimizing a neural network as in [0062]. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the optimization and training of neural networks of Lin with the optimization of target hardware and systems of Shen as they are both analogous art along with the claimed invention which teach solutions to training of neural networks, and the combination would lead to an improved system which would improve performance and simplify programming as taught in [0187] of Shen. Examiner notes Lin teaches a system with processing circuitry ([0111] CPU/system with Processor) Regarding Claims 2 and 12, Lin teaches wherein the modifying includes: modifying at least one of a topology, a computation order, a quantization parameter, or an operation parameter of an operation layer of the neural network model ([0126] operational parameters, [0136] computation orders and pairs, [0381] topology) Regarding Claims 3 and 13, Lin teaches wherein the neural network model is an untrained model before the compilation optimization information is obtained, and the modifying includes: training the neural network model based on the one or more modifications indicated by the compilation optimization information ([0111-113] training module trains the modification using the compiled information as in Claim 1 above). Regarding Claims 4 and 14, Lin teaches wherein the neural network model is a trained model before the compilation optimization information is obtained, and the modifying includes: retraining or tuning the neural network model based on the one or more modifications indicated by the compilation optimization information ([0558-559] training and retraining based on the modification and updating the machine learning model/neural network) Regarding Claims 5 and 15, Lin teaches wherein the neural network model is a trained model before the compilation optimization information is obtained, the modifying includes: calibrating the neural network model based on the one or more modifications indicated by the compilation optimization information ([0561] calibration of the machine learning model) Regarding Claims 6 and 16, Lin teaches wherein the calibrating includes: calibrating the neural network model based on the one or more modifications indicated by the compilation optimization information and calibration data including a dataset that is representable to an inference data distribution ([0561] calibration of the machine learning model using datasets as in Claims above) Regarding Claims 8 and 18, Lin does not teach the specific hardware information. Shen teaches a hardware target as in [0035] along with training, retraining, and optimizing a neural network as in [0062]. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the optimization and training of neural networks of Lin with the optimization of target hardware and systems of Shen as they are both analogous art along with the claimed invention which teach solutions to training of neural networks, and the combination would lead to an improved system which would improve performance and simplify programming as taught in [0187] of Shen. Regarding Claims 9 and 19, Lin teaches wherein the modifying includes: applying a model quantization to the neural network model based on the one or more modifications indicated by the compilation optimization information ([0141-144] quantization used in converting weights and compiling/updating optimized model) Regarding Claims 10 and 20, Lin teaches wherein the model quantization is applied during or after a training process that trains the neural network model ([0144] and [0154] quantization is applied during both the training and retraining) Allowable Subject Matter Claims 7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if the independent claim was amended in such a way as to overcome the 35 USC 101 and 103 rejections. Conclusion The prior art made of record is considered pertinent to applicant's disclosure. US 20250259388 A1 Lin; Chen-Hsuan et al. USING ONE OR MORE NEURAL NETWORKS TO GENERATE THREE-DIMENSIONAL (3D) MODELS US 20220261631 A1 Cohen; Jonathan Michael et al. PIPELINES FOR EFFICIENT TRAINING AND DEPLOYMENT OF MACHINE LEARNING MODELS US 20220180125 A1 Shen; Yichun et al. DISTRIBUTED NEURAL NETWORK TRAINING SYSTEM US 20250348737 A1 Yu; Chong ADJUSTING NEURAL NETWORK ARCHITECTURES US 20250225394 A1 Yu; Chenhan et al. MODIFYING NEURAL NETWORKS US 20250192855 A1 Cho; Yunseong et al. SIGNAL PROCESSING TECHNIQUES US 20250181889 A1 Aarts; Bastiaan Joannes Matheus et al. API FOR RECURRENT NEURAL NETWORKS US 20240320184 A1 Koker; Altug et al. MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS US 20240160905 A1 Yu; Chong TECHNIQUES FOR COMPRESSING NEURAL NETWORKS US 20230325656 A1 Li; Rundong et al. ADJUSTING PRECISION OF NEURAL NETWORK WEIGHT PARAMETERS US 20230123811 A1 Collins; Alexander James et al. TECHNIQUES FOR INFERRING INFORMATION US 20230121044 A1 Grover; Vinod et al. TECHNIQUES FOR DETERMINING DIMENSIONS OF DATA US 20230025245 A1 Grover; Vinod et al. NEURAL NETWORK EVALUATION US 20230004760 A1 Mustikovela; Siva Karthik et al. TRAINING OBJECT DETECTION SYSTEMS WITH GENERATED IMAGES US 20220044114 A1 Sriram; Parthasarathy et al. HYBRID QUANTIZATION OF NEURAL NETWORKS FOR EDGE COMPUTING APPLICATIONS US 20200082243 A1 Jin; Xiangdong et al. SUBGRAPH TILE FUSION IN A CONVOLUTIONAL NEURAL NETWORK US 20190243755 A1 Luo; Chenchi et al. DYNAMIC MEMORY MAPPING FOR NEURAL NETWORKS Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH M WAESCO whose telephone number is (571)272-9913. The examiner can normally be reached on 8 AM - 5 PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BETH BOSWELL can be reached on (571) 272-6737. The fax phone number for the organization where this application or proceeding is assigned is 571-273-1348. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH M WAESCO/Primary Examiner, Art Unit 3625B 6/27/2026
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Prosecution Timeline

Mar 21, 2024
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §101, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
47%
Grant Probability
90%
With Interview (+42.3%)
3y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 462 resolved cases by this examiner. Grant probability derived from career allowance rate.

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