DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12 and 16-20 in the reply filed on 07/15/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/11/2024 and 02/13/2025 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 10-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (2024/0194260).
Re claim 1, Chen teaches a memory component (Figs. 4-5B) comprising: an array (410) of memory strings (413) coupled to a Bit Line (BL) [62-63] and a Common Source Line (CSL) (431), the BL [62-63] and the CSL (431) enabled to transmit a plurality of signals [51]; feature logic circuitry (420); memory logic circuitry (432); a first one or more conductors (452) formed through a corresponding one or more Through-Array Vias (TAVs) (434) enabling communication between the feature logic circuitry (420) and the memory logic circuitry (432); and a second one or more conductors (414) formed to contact a corresponding one or more Through-Array Contacts (TACs) (415), wherein at least one of the plurality of signals is transmitted to at least one of the second one or more conductors [47-53].
Re claim 2, Chen teaches the memory component of claim 1, wherein the BL [62-63] is coupled to the memory logic circuitry (432) using one of the TACs (415).
Re claim 3, Chen teaches the memory component of claim 1, wherein the BL is coupled to the memory logic circuitry using direct bonding [61-63].
Re claim 4, Chen teaches the memory component of claim 1, wherein a feature logic integrated circuit die (421, 420) comprises the feature logic circuitry (420) and a memory logic integrated circuit die (411, 432) comprises the memory logic circuitry (432).
Re claim 5, Chen teaches the memory component of claim 4, wherein a memory array die (400) comprises the array of memory strings (413). Re claim 6, Chen teaches the memory component of claim 4, wherein a first operating voltage of the feature logic integrated circuit die (421, 420) is less than [45] a second operating voltage of the memory logic integrated circuit die (411, 432). Re claim 7, Chen teaches the memory component of claim 1, wherein the feature logic circuitry (420) comprises one or more of: page buffer circuitry, finite state machine circuitry, on-demand operation circuitry, Quality of Service (QoS) boosting circuitry, read/write performance improving circuitry, Input/Output (I/O) circuitry, Field Programmable Gate Array (FPGA) circuitry, one or more logic circuits enabled to operate at a lower voltage than the memory logic circuitry, and NAND interface circuitry [51].
Re claim 10, Chen teaches the memory component of claim 1, wherein the feature logic circuitry (420) comprises asynchronous independent plane operation circuitry, which is enabled to control the array of memory strings to perform at least one of (1) asynchronous independent plane program operations and (2) asynchronous independent plane erase operations [38].
Re claim 11, Chen teaches the memory component of claim 1, wherein the memory logic circuitry (432) comprises one or more of: charge pump circuitry, sense amplifier circuitry, programming circuitry, Word Line Driver (WLD) circuitry, String Select Line (SSL) driver circuitry, Ground Select Line (GSL) driver circuitry, one or more transistors coupled to a sense amplifier wherein the one or more transistors optionally comprise one or more BL clamping transistors and/or one or more BL precharge transistors, and CSL driver circuitry [64].
Re claim 12, Chen teaches the memory component of claim 1, wherein the array of memory strings (413) is implemented according to memory technology comprising one or more of: Resistive Random Access read/write Memory (ReRAM) technology, phase change memory technology, Spin-Transfer Torque Resistive Random Access read/write Memory (STT-RAM) technology, NAND-based flash memory technology, and NOR-based flash memory technology [47]. Claim(s) 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (2024/0194260).
Re claim 16, Chen teaches a memory component (Figs. 4-5B) comprising: an array (410) of memory strings (413) coupled to a Bit Line (BL) [62-63] and a Common Source Line (CSL) (431), the BL [62-63] and the CSL (431) transmitting a plurality of signals [51]; feature logic circuitry (420); memory logic circuitry (432); a first one or more conductors (452) formed through a corresponding one or more through vias (434) enabling communication between the feature logic circuitry (420) and the memory logic circuitry (432); and a second one or more conductors (414) formed to contact one or more corresponding direct bonds (415), and wherein at least one of the plurality of signals is transmitted to at least one of the second one or more conductors [49-51].
Re claim 17, Chen teaches the memory component of claim 16, wherein the through vias comprise Through- Array Vias (TAVs) (434) that extend through the array (410), and the BL and the CSL are coupled to respective ones of the second one or more conductors [62-63]. Re claim 18, Chen teaches the memory component of claim 16, wherein the through vias comprise Through- Array Vias (TAVs) (434) that extend through the array (410), and the BL is coupled to the memory logic circuitry (432) by a direct bond [61-63].
Re claim 19, Chen teaches the memory component of claim 16, wherein the through vias comprise Through-Array Vias (TAVs) (434) that extend through the array (410), and the BL is coupled to the feature logic circuitry (420) by a direct bond [61-63].
Re claim 20, Chen teaches the memory component of claim 16, wherein the through vias (434) comprise through silicon vias [49-50], and the BL and the CSL [62-63] are coupled to respective ones of the second one or more conductors (Fig. 4).
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 8, Chen teaches the memory component of claim 1, yet remains explicitly silent to wherein the feature logic circuitry comprises logic circuitry enabled to enhance performance of AI operations, which comprises any one or more of: an accumulator with shift-and-add and/or inversion operations, logic circuitry to quickly determine a count and compare the count to another value, first one or more registers enabled to retain intermediate data, and second one or more registers enabled to store input patterns.
Re claim 9, Chen teaches the memory component of claim 1, yet remains explicitly silent to wherein the feature logic circuitry comprises memory reliability circuitry, which is enabled to perform any one or more of: Cyclic Redundancy Check (CRC) operations, checksum operations, threshold voltage tracking operations, and error handling flow operations, one or more of the error handling flow operations enabling error correction according to one or more error correcting codes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached on M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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