Prosecution Insights
Last updated: August 17, 2026
Application No. 18/612,648

SEMICONDUCTOR PACKAGE

Non-Final OA §112
Filed
Mar 21, 2024
Priority
Mar 24, 2023 — RE 10-2023-0039224 +1 more
Examiner
CHANG, JAY C
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
568 granted / 667 resolved
+25.2% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
702
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
42.3%
+2.3% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
27.3%
-12.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 667 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites “a metal layer” in line 3 of the claim, however “a metal layer” element was already introduced earlier in line 4 of claim 1, which claim 5 depends from, and thereby it is unclear whether the “a metal layer” in line 3 of the claim is directed to that same element and therefore should be properly amended to “the metal layer” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element. Claim 6 recites the limitation “wherein second width thereof” in line 2 od the claim, however it is unclear which specific element is “thereof” in reference of. The Examiner suggests amending the limitation to clearly identify which element is associated with the claimed “second widths”. Allowable Subject Matter Claims 1-4 and 7-20 are allowed. Regarding independent claim 1, Figures 1-3 of Park et al. (US 2021/0407949 A1, hereinafter “Park”) disclose a semiconductor package comprising: a first substrate 110 (“substrate”- ¶0023); a first pattern 180 (“pad”- ¶0018, specifically the 180 at the outermost positions) and a second pattern 180 (“pad”- ¶0018, specifically the 180 at the inner positions) disposed on the first substrate 110; a semiconductor chip 200 (“stack… chip”- ¶0022) disposed on the first substrate 110 and comprising a metal layer 250 (“TSV”, which comprises metal- ¶0034); a circuit structure 224c (“lines”- ¶0032) disposed on an underside of the metal layer 250 of the semiconductor chip 200; and a plurality of first bumps 195, 290 (“bump”- ¶0018) disposed between the first substrate 110 and the semiconductor chip 200 and electrically connected to the first pattern 180, wherein the first pattern 180 comprises a ground pattern or a power pattern, since 180 is connected to semiconductor devices and thereby would carry a voltage (i.e., power) (¶¶0026, 0041), the first substrate 110 includes a first region overlapping the circuit structure 224c in a vertical direction, and the plurality of first bumps 195, 290 are disposed adjacent to the first region on a top surface of the first substrate 110. Park does not expressly disclose a first bump of the plurality of first bumps has an elongated shape substantially parallel to an adjacent side of the first region. Thus, regarding independent claim 1, the claim is allowed, because the prior art of record including Park, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a first bump of the plurality of first bumps has an elongated shape substantially parallel to an adjacent side of the first region”. Claims 2-4 and 7-11 are allowed as being dependent on allowed claim 1. Regarding independent claim 12, Figures 1-3 of Park disclose a semiconductor package comprising: a first substrate 110 (“substrate”- ¶0023); a first pattern 180 (“pad”- ¶0018, specifically the 180 at the outermost positions) and a second pattern 180 (“pad”- ¶0018, specifically the 180 at the inner positions) disposed on the first substrate 110; a semiconductor chip 200 (“stack… chip”- ¶0022) disposed on the first substrate 110 and comprising a semiconductor substrate 210 (“semiconductor layer”- ¶0023), a device layer 224a (“lines”- ¶0032), and a metal layer 250 (“TSV”, which comprises metal- ¶0034); a circuit structure 224c (“lines”- ¶0032) disposed on an underside of the metal layer 250 of the semiconductor chip 200; and a plurality of first bumps 195, 290 (“bump”- ¶0018) disposed between the first substrate 110 and the semiconductor chip 200 and electrically connected to the first pattern 180, wherein the semiconductor chip 200 is disposed on the first substrate 110 such that the metal layer 250 faces the first substrate 110, the metal layer 250 comprises a wiring metal (¶0034), and the circuit structure 224c is exposed toward the first substrate 110 from the wiring metal, the first pattern 180 comprises a ground pattern or a power pattern, since 180 is connected to semiconductor devices and thereby would carry a voltage (i.e., power) (¶¶0026, 0041), the first substrate 110 includes a first region overlapping the circuit structure 224c in a vertical direction, and the plurality of first bumps 195, 290 are disposed adjacent to the first region on a top surface of the first substrate 110. Park does not expressly disclose a first bump of the plurality of first bumps has an elongated shape substantially parallel to an adjacent side of the first region. Thus, regarding independent claim 12, the claim is allowed, because the prior art of record including Park, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a first bump of the plurality of first bumps has an elongated shape substantially parallel to an adjacent side of the first region”. Claims 13-17 are allowed as being dependent on allowed claim 12. Regarding independent claim 18, Figures 1-3 of Park disclose a semiconductor package comprising: a first substrate 110 (“substrate”- ¶0023); a first pattern 180 (“pad”- ¶0018, specifically the 180 at the outermost positions) and a second pattern 180 (“pad”- ¶0018, specifically the 180 at the inner positions) disposed on the first substrate 110; a semiconductor chip 200 (“stack… chip”- ¶0022) disposed on the first substrate 110 and comprising a semiconductor substrate 210 (“semiconductor layer”- ¶0023), a device layer 224a (“lines”- ¶0032), and a metal layer 250 (“TSV”, which comprises metal- ¶0034); a circuit structure 224c (“lines”- ¶0032) disposed on an underside of the metal layer 250; a plurality of first bumps 195, 290 (“bump”- ¶0018, specifically the bumps on the 180 at the outermost positions) positioned between the first substrate 110 and the semiconductor chip 200 and electrically connected to the first pattern 180; and a plurality of second bumps 195, 290 (“bump”- ¶0018, specifically the bumps on the 180 at the inner positions) located between the first substrate 110 and the semiconductor chip 200 and electrically connected to the second pattern 180, wherein the semiconductor chip 200 is disposed on the first substrate 110 such that the metal layer 250 faces the first substrate 110, the metal layer 250 comprises a wiring metal (¶0034), and the circuit structure 224c is exposed toward the first substrate 110 from the wiring metal, the first pattern 180 comprises a ground pattern or a power pattern, and the second pattern 180 comprises a ground pattern, a power pattern, or a signal pattern, since 180 is connected to semiconductor devices and thereby would carry a voltage (i.e., power) (¶¶0026, 0041), the first substrate 110 includes a first region overlapping the circuit structure 224c in a vertical direction, and the plurality of first bumps 180 are disposed adjacent to sides of the first region on a top surface of the first substrate 110. Park does not expressly disclose a first bump of the plurality of first bumps has a first width and a second width that is greater than the first width in a direction perpendicular to the first width and is disposed on the top surface of the first substrate such that the second width is substantially parallel to the first region and the plurality of first bumps at least partially surrounding the first region. Thus, regarding independent claim 18, the claim is allowed, because the prior art of record including Park, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a first bump of the plurality of first bumps has a first width and a second width that is greater than the first width in a direction perpendicular to the first width and is disposed on the top surface of the first substrate such that the second width is substantially parallel to the first region and the plurality of first bumps at least partially surrounding the first region”. Claims 19-20 are allowed as being dependent on allowed claim 18. Claims 5-6 (which depend from allowed claim 1) would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Cho et al. (US 2018/0337120 A1), which discloses a semiconductor package comprising a plurality of bumps connecting a semiconductor chip to a substrate. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 21, 2024
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+14.0%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 667 resolved cases by this examiner. Grant probability derived from career allowance rate.

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