Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on July 24, 2026, regarding the application filed March 21, 2024.
Election/Restrictions
Applicant’s election without traverse of Species I, corresponding to the embodiment shown in FIG. 18, on which claims 1-8 and 10-20 are readable, in the reply filed on July 24, 2026, is acknowledged. Claim 9 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-20 are pending, with claim 9 currently withdrawn from consideration.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on Korean Patent Application No. 10-2023-0063250, filed on May 16, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-039150, filed on March 24, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 21, 2024 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on March 21, 2024 are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Seong et al., US 2021/0193664 A1 (hereinafter Seong) in view of Lee et al., US 2020/0287013 A1 (hereinafter Lee).
Regarding claim 1, Seong discloses: A method of manufacturing a semiconductor device, the method comprising: preparing a substrate (Seong, substrate 110, [0025]) comprising a plurality of active regions (Seong, FIG. 1, plurality of active regions 118, ACT, [0014]) and a peripheral active region (Seong, peripheral circuit region PR, including logic active regions 117, ACTP, [0014; 0027]; Applicant’s specification states that the peripheral region includes logic cells, see [0029]) defined by an isolation layer (Seong, FIG. 1, device isolation structure, including logic device isolation layer 115 in the peripheral circuit region PR, [0026; 0028])
forming a word line (Seong, word lines 120, [0033]) in a word line trench (Seong, word lines 120 formed in word line trenches 120T, [0031]) that crosses the plurality of active regions (Seong, FIG. 4D, word line trenches 120T arranged at equal intervals across the active regions 118, [0030]);
forming a plurality of bit line structures (Seong, bit line structures 140, [0045]), each of the plurality of bit line structures comprising a bit line (Seong, bit lines 147, [0045]) on the plurality of active regions (Seong, FIG. 1, FIG. 4D, “bit line structures 140 including a plurality of bit lines 147 and a plurality of insulation capping lines 148 may each extend lengthwise in the second horizontal direction (Y direction) parallel to the main surface of the substrate 110,” [0045]),
forming a plurality of gate line structures (Seong, gate line structures 140P, [0052]), each of the plurality of gate line structures comprising a gate line (Seong, FIG. 4F, gate line 147P, [0052]) on the peripheral active region (Seong, FIG. 4G shows gate lines 147P [the gate line] formed on logic active region 117 [the peripheral active region]);
forming a plurality of buried contacts between the plurality of bit line structures (Seong, FIGs. 5A-5G, buried contacts 170; “a plurality of buried contacts BC may be formed between two adjacent bit lines BL,” [0017]), the plurality of buried contacts being connected to the plurality of active regions (Seong, FIGs. 5A-5G, buried contacts 170 [the buried contacts] extend from active region 118 [the active region], [0057]);
forming an inter-gate insulating layer between the plurality of gate line structures (Seong, FIGs. 5A-5G, first filling insulation layer 172, [0061]), the inter-gate insulating layer comprising an oxide (Seong, “the first filling insulation layer 172 may include oxide,” [0061])
forming a gate cover insulating layer at least partially covering the plurality of gate line structures and the inter-gate insulating layer (Seong, FIG. 5F, second filling insulation layer 174, [0061]);
forming a peripheral contact plug (Seong, FIGs. 6F, 9F, logic active region contact plug CPF formed in logic active region contact holes CPHF, [0065; 0079]), connected to the peripheral active region through the gate cover insulating layer and the inter-gate insulating layer (Seong, FIG. 9F shows logic active region contact plug CPF [the peripheral contact plug] connected to logic active region 117 [the peripheral active region] through first and second filling insulation layers 172 and 174 [the gate cover insulating layer and the inter-gate insulating layer], [0084]);
forming a plurality of landing pads on the plurality of buried contacts (Seong, FIGs. 9A-9G, “The plurality of landing pads 190 may be arranged on the plurality of buried contacts 170,” [0077]);
forming a peripheral bit line on the peripheral contact plug (Seong, FIG. 11, logic bit lines BLP [the peripheral bit line] formed on logic active region contact plug CPF [the peripheral contact plug], [0079]); and
forming a plurality of capacitor structures on the plurality of landing pads (Seong, FIGs. 10A-10D, capacitor structures 200, “a plurality of capacitor structures 200 may be formed by sequentially forming a plurality of lower electrodes 210, a capacitor dielectric layer 220, and an upper electrode 230 on the plurality of landing pads 190,” [0087]).
Although Seong discloses the inter-gate insulating layer comprises an oxide, Seong is silent insofar as the oxide having impurities.
However, Lee, in the same field of endeavor, teaches that an insulating layer having impurities provides improved characteristics such as reduced current leakage (Lee, FIG. 11A, high-k dielectric layer HK, doped with impurities DPT, “because the high-k dielectric layer HK includes the impurities DPT uniformly distributed therein, it may be possible to prevent current leakage through the high-k dielectric layer HK and to improve characteristics of the high-k dielectric layer HK ,” [0060]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Seong with the teachings of Lee, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Lee, to prevent current leakage, thereby improving device performance and reliability.
Regarding claim 2, Seong in view of Lee teaches: The method of claim 1, wherein the forming of the inter-gate insulating layer (Seong, FIGs. 5A-5G, first filling insulation layer 172, [0061]) comprises positioning top surfaces of the plurality of gate line structures (Seong, FIG. 5F, top surface of gate line structures 140P, [0052]) and a top surface of the inter-gate insulating layer (Seong, FIG. 5F, top surface of first filling insulation layer 172, [0061]) at a same vertical level such that the top surfaces of the plurality of gate line structures and the top surface of the inter-gate insulating layer are coplanar (Seong, see FIG. 5F, top surface of the first filling insulation layer 172 [the inter-gate insulating layer] at the same vertical level as the top surface of each gate line structure 140P [the plurality of gate line structures], i.e., coplanar; “top surface of the filling insulation layer (including first and second filling insulation layers 172 and 174) … may be at the same level as the top surface of each gate line structure 140P,” [0061]).
Regarding claim 4, Seong in view of Lee teaches: The method of claim 1, wherein the impurities comprise nitrogen, phosphorus, or “The impurities DPT [the impurities] may be selected from the group consisting of nitrogen (N), fluorine (F), phosphorous (P), boron (B), and a combination thereof,” (Lee, [0081]; [0053]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Lee include one or more of Applicant’s claimed alternative elements, for example: nitrogen, phosphorus.
Regarding claim 5, Seong in view of Lee teaches: The method of claim 4, wherein the impurities comprise nitrogen (Lee, FIG. 11A, high-k dielectric layer HK [analogous to the inter-gate insulating layer], doped with impurities DPT impurities DPT, nitrogen (N), [0053; 0081]), and wherein an atomic ratio of nitrogen among nitrogen and oxygen in the inter-gate insulating layer is about 10% to about 30% (Lee, impurity concentration, i.e., nitrogen concentration, adjusted to have a range from 0.1% to 20%, [0081]).
Regarding claim 6, Seong in view of Lee teaches: The method of claim 4, wherein the impurities comprise phosphorus (Lee, FIG. 11A, high-k dielectric layer HK [analogous to the inter-gate insulating layer], doped with impurities DPT, “The impurities DPT [the impurities] may be selected from the group consisting of nitrogen (N), fluorine (F), phosphorous (P), boron (B), and a combination thereof,” [0081]; [0053])or (Lee, impurity concentration, i.e., phosphorus concentration, adjusted to have a range from 0.1% to 20%, [0081]),
The alternative elements taught by Lee include one or more of Applicant’s claimed alternative elements, for example: phosphorus.
Regarding claim 7, Seong in view of Lee teaches: The method of claim 1, wherein the peripheral contact plug has a substantially constant horizontal width and extends in a vertical direction (Seong, FIGs. 6F, 9F, show logic active region contact plug CPF [the peripheral contact plug] formed with a substantially constant horizontal width and extends in a vertical direction, [0065; 0079]). The limitation a substantially constant horizontal width is sufficiently broad so as to encompass the minor variations in width of the logic active region contact plug CPF [the peripheral contact plug] taught by Seong.
Regarding claim 8, Seong in view of Lee teaches: The method of claim 1, further comprising, prior to forming the peripheral contact plug (Seong, FIGs. 6F, 9F, logic active region contact plug CPF), forming a contact spacer (Seong, FIG. 6E, gate insulation spacer 150P, [0053]), wherein the contact spacer surrounds at least a portion of an outer surface of the peripheral contact plug (Seong, FIG. 7F shows gate insulation spacer 150P [the contact spacer] surrounds logic active region contact plug CPHF [the peripheral contact plug] after filling contact hole CPHE).
Regarding claim 10, Seong in view of Lee teaches: The method of claim 1, further comprising, prior to forming the peripheral contact plug (Seong, FIGs. 6F, 9F, logic active region contact plug CPF), forming a contact spacer (Seong, FIG. 6E, gate insulation spacer 150P, [0053]), (Seong, FIG. 7F shows gate insulation spacer 150P [the contact spacer] surrounds logic active region contact plug CPHF [the peripheral contact plug] after filling contact hole CPHE), and wherein the peripheral contact plug has a substantially constant horizontal width and extends in a vertical direction (Seong, FIGs. 6F, 9F, show logic active region contact plug CPF [the peripheral contact plug] formed with a substantially constant horizontal width and extends in a vertical direction, [0065; 0079]). The limitation a substantially constant horizontal width is sufficiently broad so as to encompass the minor variations in width of the logic active region contact plug CPHF [the peripheral contact plug] taught by Seong.
Seong in view of Lee is silent regarding: wherein a portion of a space defined by peripheral contact hole that passes through the inter-gate insulating layer has an entasis shape.
However, given the teachings of Seong and Lee, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to try the limited number of variations in width of the peripheral contact plug in order to arrive at Applicant’s claimed wherein a portion of a space defined by peripheral contact hole that passes through the inter-gate insulating layer has an entasis shape with a high likelihood of success and without undue experimentation. Furthermore, because Applicant’s specification does not indicate that the claimed entasis shape, or variation in width, is critical or unexpected, the selection of an appropriate width would be an obvious matter of design choice for one of ordinary skill (MPEP 2144.04).
Claims 3 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Seong in view of Lee and further in view of Kim et al., US 2009/0098740 A1 (hereinafter Kim).
Regarding claim 3, Seong in view of Lee teaches: The method of claim 2. Seong in view of Lee is silent regarding: wherein the forming of the inter-gate insulating layer further comprises: forming a preliminary inter-gate insulating layer at least partially filling spaces between the plurality of gate line structures and at least partially covering top surfaces of the plurality of gate line structures, the preliminary inter-gate insulating layer comprising an oxide having the impurities; and removing an upper portion of the preliminary inter-gate insulating layer such that the plurality of gate line structures are exposed.
Although Seong discloses forming an inter-gate insulating layer comprises an oxide, Seong is silent regarding: forming a preliminary inter-gate insulating layer at least partially filling spaces between the plurality of gate line structures and at least partially covering top surfaces of the plurality of gate line structures, the preliminary inter-gate insulating layer comprising an oxide having the impurities; and removing an upper portion of the preliminary inter-gate insulating layer such that the plurality of gate line structures are exposed.
However, Lee, in the same field of endeavor, teaches that an insulating layer having impurities provides improved characteristics such as reduced current leakage (Lee, FIG. 11A, high-k dielectric layer HK, doped with impurities DPT, “because the high-k dielectric layer HK includes the impurities DPT uniformly distributed therein, it may be possible to prevent current leakage through the high-k dielectric layer HK and to improve characteristics of the high-k dielectric layer HK ,” [0060]). “The impurities DPT [the impurities] may be selected from the group consisting of nitrogen (N), fluorine (F), phosphorous (P), boron (B), and a combination thereof,” (Lee, [0081]; [0053]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Seong with the teachings of Lee, selecting appropriate impurities from the known finite options, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Lee, to prevent current leakage, thereby improving device performance and reliability.
Seong in view of Lee is silent regarding: forming a preliminary inter-gate insulating layer at least partially filling spaces between the plurality of gate line structures and at least partially covering top surfaces of the plurality of gate line structures … and removing an upper portion of the preliminary inter-gate insulating layer such that the plurality of gate line structures are exposed.
However, such a method of forming an insulating layer was known in the art before the effective filing date of the claimed invention. For example, Kim, in the same field of endeavor, teaches forming an insulating layer between and at least partially covering gate structures (Kim, FIG. 2D, second insulating layer 212 [the preliminary inter-gate insulating layer] shown between and partially covering gate structures, [0031]), and subsequently removing the upper portion of the insulating layer such that the plurality of gate line structures are exposed, (Kim, see FIG. 2E, [0033]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Seong and Lee with the teachings of Kim, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kim, to enhance strength of the insulating layers to prevent etchant from damaging or forming a void during subsequent processing steps (Kim, [0034]), thereby improving manufacturing yield, device performance, and reliability.
Regarding claim 11, Seong discloses: A method of manufacturing a semiconductor device, the method comprising: forming, on a substrate (Seong, substrate 110, [0025]), a plurality of gate line structures, each of the plurality of gate line structures comprising a gate line (Seong, FIG. 4G shows gate lines 140P [the gate line structures] comprised of gate lines 147P [the gate line] formed on substrate 110, [0052]);
forming an inter-gate insulating layer (Seong, FIGs. 5A-5G, first filling insulation layer 172, [0061]) comprising an oxide (Seong, “the first filling insulation layer 172 may include oxide,” [0061])
forming a gate cover insulating layer at least partially covering the plurality of gate line structures and the inter-gate insulating layer (Seong, FIGs. 5A-5G, second filling insulation layer 174, [0061]);
forming a peripheral contact hole through the gate cover insulating layer and the inter-gate insulating layer (Seong, FIG. 9F shows logic active region contact plug CPF [the peripheral contact plug] connected to logic active region 117 [the peripheral active region] through first and second filling insulation layers 172 and 174 [the inter-gate insulating layer and the gate cover insulating layer], [0084]), the substrate being exposed at a bottom of the peripheral contact hole (Seong, FIG. 6F, contact hole CPHF, [0063]); and
forming a peripheral contact plug at least partially filling the peripheral contact hole (Seong, FIGs. 6F, 9F, logic active region contact plug CPF formed in logic active region contact holes CPHF, [0065; 0079]).
Although Seong discloses forming an inter-gate insulating layer comprises an oxide, Seong is silent regarding: forming a preliminary inter-gate insulating layer at least partially filling spaces between the plurality of gate line structures and at least partially covering top surfaces of the plurality of gate line structures, the preliminary inter-gate insulating layer comprising an oxide having first impurities … forming an inter-gate insulating layer comprising an oxide having second impurities by removing an upper portion of the preliminary inter-gate insulating layer such that the plurality of gate line structures are exposed.
However, Lee, in the same field of endeavor, teaches that an insulating layer having impurities provides improved characteristics such as reduced current leakage (Lee, FIG. 11A, high-k dielectric layer HK, doped with impurities DPT, “because the high-k dielectric layer HK includes the impurities DPT uniformly distributed therein, it may be possible to prevent current leakage through the high-k dielectric layer HK and to improve characteristics of the high-k dielectric layer HK ,” [0060]). “The impurities DPT [the impurities] may be selected from the group consisting of nitrogen (N), fluorine (F), phosphorous (P), boron (B), and a combination thereof,” (Lee, [0081]; [0053]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Seong with the teachings of Lee, selecting appropriate impurities from the known finite options, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Lee, to prevent current leakage, thereby improving device performance and reliability.
Seong in view of Lee is silent regarding: forming a preliminary inter-gate insulating layer at least partially filling spaces between the plurality of gate line structures and at least partially covering top surfaces of the plurality of gate line structures … forming an inter-gate insulating layer … by removing an upper portion of the preliminary inter-gate insulating layer such that the plurality of gate line structures are exposed.
However, such a method of forming an insulating layer was known in the art before the effective filing date of the claimed invention. For example, Kim, in the same field of endeavor, teaches forming an insulating layer between and at least partially covering gate structures (Kim, FIG. 2D, second insulating layer 212 [the preliminary inter-gate insulating layer] shown between and partially covering gate structures, [0031]), and subsequently removing the upper portion of the insulating layer such that the plurality of gate line structures are exposed, (Kim, see FIG. 2E, [0033]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Seong and Lee with the teachings of Kim, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kim, to enhance strength of the insulating layers to prevent etchant from damaging or forming a void during subsequent processing steps (Kim, [0034]), thereby improving manufacturing yield, device performance, and reliability.
Regarding claim 12, Seong in view of Lee and further in view of Kim teaches: The method of claim 11, wherein the first impurities of the oxide of the preliminary inter-gate insulating layer comprise nitrogen (Lee, FIG. 11A, high-k dielectric layer HK [analogous to the inter-gate insulating layer], doped with impurities DPT impurities DPT, nitrogen (N), [0053; 0081]) and oxygen (Seong, “the first filling insulation layer 172 may include oxide,” i.e., oxygen, [0061]), and wherein an atomic ratio of nitrogen among the nitrogen and the oxygen in the oxide of the preliminary inter-gate insulating layer is about 10% to about 30% (Lee, impurity concentration, i.e., nitrogen concentration, adjusted to have a range from 0.1% to 20%, [0081]).
Regarding claim 13, Seong in view of Lee and further in view of Kim teaches: The method of claim 11, wherein, in the forming of the peripheral contact plug (Seong, FIGs. 6F, 9F, logic active region contact plug CPF formed in logic active region contact holes CPHF, [0065; 0079]), the peripheral contact plug comprises a predetermined horizontal width (Seong, see FIGs. 6E, 6F, 9F, width of peripheral contact plug determined by width of peripheral contact holes, i.e., a predetermined horizontal width) and extends in a vertical direction (Seong, FIGs. 6F, 9F, show logic active region contact plug CPF [the peripheral contact plug] extends in a vertical direction, [0065; 0079]).
Regarding claim 14, Seong in view of Lee and further in view of Kim teaches: The method of claim 13, wherein, in the forming of the peripheral contact hole (Seong, FIGs. 6E, 6F, 9F, logic active region contact holes CPHF, [0065; 0079]), the peripheral contact hole comprises a predetermined horizontal width and extends in a vertical direction (Seong, see FIGs. 6A-6G, logic active region contact holes CPHF [the peripheral contact hole] formed by etching process, i.e., a predetermined horizontal width, [0063-0068]).
Regarding claim 15, Seong in view of Lee and further in view of Kim teaches: The method of claim 13. Seong in view of Lee and further in view of Kim is silent regarding: wherein, in the forming of the peripheral contact hole, a portion of a space defined by the peripheral contact hole and that passes through the inter-gate insulating layer has an entasis shape.
However, given the teachings of Seong, Lee, and Kim, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to try the limited number of variations in width of the peripheral contact plug in order to arrive at Applicant’s claimed wherein, in the forming of the peripheral contact hole, a portion of a space defined by the peripheral contact hole and that passes through the inter-gate insulating layer has an entasis shape with a high likelihood of success and without undue experimentation. Furthermore, because Applicant’s specification does not indicate that the claimed entasis shape, or variation in width, is critical or unexpected, the selection of an appropriate width would be an obvious matter of design choice for one of ordinary skill (MPEP 2144.04).
Regarding claim 16, Seong in view of Lee and further in view of Kim teaches: The method of claim 15, further comprising, prior to forming the peripheral contact plug (Seong, FIGs. 6F, 9F, logic active region contact plug CPF), forming a contact spacer (Seong, FIG. 6E, gate insulation spacer 150P, [0053]), wherein the contact spacer surrounds at least a portion of an outer surface of the peripheral contact plug (Seong, FIG. 7F shows gate insulation spacer 150P [the contact spacer] surrounds logic active region contact plug CPHF [the peripheral contact plug] after filling contact hole CPHE).
Regarding claim 17, Seong in view of Lee and further in view of Kim teaches: The method of claim 11, wherein the forming of the inter-gate insulating layer (Seong, FIGs. 5A-5G, first filling insulation layer 172, [0061]) comprises removing an upper portion of the preliminary inter-gate insulating layer such that top surfaces of the plurality of gate line structures and a top surface of the inter-gate insulating layer are at a same vertical level and are coplanar (Kim, FIGs. 2D, 2E, [0034]; Seong, see FIG. 5F, top surface of the first filling insulation layer 172 [the inter-gate insulating layer] at the same vertical level as the top surface of each gate line structure 140P [the plurality of gate line structures], i.e., coplanar; “top surface of the filling insulation layer (including first and second filling insulation layers 172 and 174) … may be at the same level as the top surface of each gate line structure 140P,” [0061]).
Regarding claim 18, Seong discloses: A method of manufacturing a semiconductor device, the method comprising: preparing a substrate (Seong, substrate 110, [0025]) in which a plurality of active regions (Seong, FIG. 1, plurality of active regions 118, ACT, [0014]) and a peripheral active region (Seong, peripheral circuit region PR, including logic active regions 117, ACTP, [0014; 0027]) are defined by an isolation layer (Seong, FIG. 1, device isolation structure, including logic device isolation layer 115 in the peripheral circuit region PR, [0026; 0028]);
forming a word line trench by removing portions of the isolation layer and portions of each of the plurality of active regions (Seong, FIG. 4D, word line trenches 120T), the word line trench crossing the plurality of active regions in the substrate and extending in a first horizontal direction (Seong, FIG. 4D, word line trenches 120T arranged at equal intervals across the active regions 118, [0030]);
forming a word line in the word line trench (Seong, word lines 120 formed in word line trenches 120T, [0031]);
forming a plurality of bit line structures (Seong, bit line structures 140, [0045]) extending parallel to each other in a second horizontal direction orthogonal to the first horizontal direction on the plurality of active regions (Seong, FIG. 1, FIG. 4D, “bit line structures 140 including a plurality of bit lines 147 and a plurality of insulation capping lines 148 may each extend lengthwise in the second horizontal direction (Y direction) parallel to the main surface of the substrate 110,” [0045]);
forming a plurality of gate line structures (Seong, gate line structures 140P, [0052]), each of the plurality of gate line structures comprising a gate line (Seong, FIG. 4F, gate line 147P, [0052]) on the peripheral active region (Seong, FIG. 4G shows gate lines 147P [the gate line] formed on logic active region 117 [the peripheral active region]);
forming a plurality of buried contacts between the plurality of bit line structures (Seong, FIGs. 5A-5G, buried contacts 170; “a plurality of buried contacts BC may be formed between two adjacent bit lines BL,” [0017]), the plurality of buried contacts being connected to the plurality of active regions (Seong, FIGs. 5A-5G, buried contacts 170 [the buried contacts] extend from active region 118 [the active region], [0057]);
forming an inter-gate insulating layer (Seong, FIGs. 5A-5G, first filling insulation layer 172, [0061]) (Seong, “the first filling insulation layer 172 may include oxide,” [0061])
forming a gate cover insulating layer at least partially covering the plurality of gate line structures and the inter-gate insulating layer (Seong, FIGs. 5A-5G, second filling insulation layer 174, [0061]);
forming a first peripheral contact hole (Seong, FIGs. 6A-6G, contact hole CPHF, [0063]) through the gate cover insulating layer and the inter-gate insulating layer, the peripheral active region being exposed at a bottom of the first peripheral contact hole (Seong, FIGs. 6A-6G, contact hole CPHF [the first peripheral contact hole] formed through second filling insulation layer 174 [the gate cover insulation], first filling insulation layer 172 [the inter-gate insulating layer]; FIG. 6F shows logic active region 117 [the peripheral active region] exposed at a bottom of contact hole CPHF [the first contact hole], [0065]);
forming a second peripheral contact hole (Seong, FIGs. 6A-6G, contact hole CPHG, [0063]) through the gate cover insulating layer, wherein at least one gate line of the plurality of gate line structures is exposed at a bottom of the second peripheral contact hole (Seong, FIGs. 6A-6G, contact hole CPHG [the second peripheral contact hole] formed through second filling insulation layer 174 [the gate cover insulation]; FIG. 6G shows gate lines 147P [the gate line] exposed at a bottom of contact hole CPHG [the second peripheral contact hole], [0066]);
forming a preliminary contact material layer (Seong, FIGs. 8A-8G, landing pad material layer 190P, [0071]) at least partially filling the first peripheral contact hole and the second peripheral contact hole (Seong, FIGs. 8A-8G, “landing pad material layer 190P [the preliminary contact material] is formed to fill the plurality of landing pad holes 190H and the plurality of contact holes CPHE, CPHF [the first peripheral contact holes], and CPHG [the second peripheral contact holes],” [0071]) and at least partially covering a top surface of the gate cover insulating layer (Seong, FIGs. 8A-8G show landing pad material layer 190P [the preliminary contact material] covering a top surface of second filling insulation layer 174 [the gate cover insulating layer);
forming a first peripheral contact plug (Seong, FIG. 9F shows logic active region contact plug CPF [the first peripheral contact plug] connected to logic active region 117 [the peripheral active region], [0071; 0084]) and a second peripheral contact plug at least partially filling the first peripheral contact hole and the second peripheral contact hole, respectively (Seong, FIGs. 9A-9G shows logic active region contact plug CPF [the first peripheral contact plug] and gate line contact plug CPG1 [the second peripheral contact plug] at least partially filling the contact holes CPHF [the first peripheral contact holes], and CPHG [the second peripheral contact holes], [0080]), by removing an upper portion of the preliminary contact material layer (Seong, “a plurality of contact plugs CPE, CPF [the first peripheral contact plugs], and CPG [the second peripheral contact plugs] respectively filling the plurality of contact holes CPHE, CPHF [the first peripheral contact hole], and CPHG [the second peripheral contact hole] are formed by removing the portions of the landing pad material layer 190P [the preliminary contact material layer],” [0079]);
forming a plurality of landing pads on the plurality of buried contacts (Seong, FIGs. 9A-9G, “The plurality of landing pads 190 may be arranged on the plurality of buried contacts 170,” [0077]);
forming a peripheral bit line on each of the first peripheral contact plug and the second peripheral contact plug (Seong, FIGs. 9A-9G, bit line structure 140 [the peripheral bit line] shown formed on each of contact plug CPF [the first peripheral contact plug] and gate line contact plug CPG1 [the second peripheral contact plug]); and
forming a plurality of capacitor structures on the plurality of landing pads (Seong, FIGs. 10A-10D, capacitor structures 200, “a plurality of capacitor structures 200 may be formed by sequentially forming a plurality of lower electrodes 210, a capacitor dielectric layer 220, and an upper electrode 230 on the plurality of landing pads 190,” [0087]),
wherein the first peripheral contact plug has a substantially constant horizontal width and extends in a vertical direction (Seong, FIGs. 6F, 9F, show logic active region contact plug CPF [the first peripheral contact plug] formed with a substantially constant horizontal width and extends in a vertical direction, [0065; 0079]). The limitation a substantially constant horizontal width is sufficiently broad so as to encompass the minor variations in width of the logic active region contact plug CPF [the peripheral contact plug] taught by Seong.
Although Seong discloses forming an inter-gate insulating layer comprises an oxide, Seong is silent regarding: forming a preliminary inter-gate insulating layer at least partially filling spaces between the plurality of gate line structures and at least partially covering top surfaces of the plurality of gate line structures, the preliminary inter-gate insulating layer comprising an oxide having first impurities comprising nitrogen … forming an inter-gate insulating layer … having second impurities comprising nitrogen.
However, Lee, in the same field of endeavor, teaches that an insulating layer having impurities provides improved characteristics such as reduced current leakage (Lee, FIG. 11A, high-k dielectric layer HK, doped with impurities DPT, “because the high-k dielectric layer HK includes the impurities DPT uniformly distributed therein, it may be possible to prevent current leakage through the high-k dielectric layer HK and to improve characteristics of the high-k dielectric layer HK ,” [0060]). “The impurities DPT [the impurities] may be selected from the group consisting of nitrogen (N), fluorine (F), phosphorous (P), boron (B), and a combination thereof,” (Lee, [0081]; [0053]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Seong with the teachings of Lee, selecting nitrogen impurities from the known finite options, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Lee, to prevent current leakage, thereby improving device performance and reliability.
Seong in view of Lee is silent regarding: forming a preliminary inter-gate insulating layer at least partially filling spaces between the plurality of gate line structures and at least partially covering top surfaces of the plurality of gate line structures … forming an inter-gate insulating layer … by removing an upper portion of the preliminary inter-gate insulating layer such that the plurality of gate line structures are exposed.
However, such a method of forming an insulating layer was known in the art before the effective filing date of the claimed invention. For example, Kim, in the same field of endeavor, teaches forming an insulating layer between and at least partially covering gate structures (Kim, FIG. 2D, second insulating layer 212 [the preliminary inter-gate insulating layer] shown between and partially covering gate structures, [0031]), and subsequently removing the upper portion of the insulating layer such that the plurality of gate line structures are exposed, (Kim, see FIG. 2E, [0033]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Seong and Lee with the teachings of Kim, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kim, to enhance strength of the insulating layers to prevent etchant from damaging or forming a void during subsequent processing steps (Kim, [0034]), thereby improving manufacturing yield, device performance, and reliability.
Regarding claim 19, Seong in view of Lee and further in view of Kim teaches: The method of claim 18, further comprising, prior to forming the preliminary contact material layer, forming a contact spacer (Seong, FIG. 6E, gate insulation spacer 150P, [0053]) covering at least a portion of an inner surface of the first peripheral contact hole, wherein, in the forming of the first peripheral contact plug and the second peripheral contact plug, the contact spacer surrounds at least a portion of an outer surface of the first peripheral contact plug (Seong, FIG. 7F shows gate insulation spacer 150P [the contact spacer] surrounds logic active region contact plug CPHF [the peripheral contact plug] after filling contact hole CPHE).
Regarding claim 20, Seong in view of Lee and further in view of Kim teaches: The method of claim 18, wherein the forming of the inter-gate insulating layer (Seong, FIGs. 5A-5G, first filling insulation layer 172, [0061]) comprises positioning top surfaces of the plurality of gate line structures and a top surface of the inter-gate insulating layer at a same vertical level, such that the top surfaces of the plurality of gate line structures and the top surface of the inter-gate insulating layer are coplanar (Kim, FIGs. 2D, 2E, [0034]; Seong, see FIG. 5F, top surface of the first filling insulation layer 172 [the inter-gate insulating layer] at the same vertical level as the top surface of each gate line structure 140P [the plurality of gate line structures], i.e., coplanar; “top surface of the filling insulation layer (including first and second filling insulation layers 172 and 174) … may be at the same level as the top surface of each gate line structure 140P,” [0061]), and wherein a top surface of each of the plurality of landing pads and a top surface of the peripheral bit line are positioned at a same vertical level (Seong, FIG. 9A shows an upper surface, i.e., a top surface, of each of landing pads 190 [the landing pads] and an upper surface, i.e., a top surface, of bit line structure 140 [the peripheral bit line] positioned at a same vertical level).
Conclusion
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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