DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant’s election without traverse of Species I, FIG. 2, and Claims 1-20 in the reply filed on June 22, 2026 is acknowledged. However, Claims 11 and 19 appear to read on non-elected Species II, FIG. 9, regarding the plurality of third upper wiring patterns respectively between the pair of first upper wiring patterns as disclosed in [0084] of the Specification. Thus, Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 22, 2026.
Specification
The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 1, the limitation “a lower solder resist layer (212) covering an upper surface of the lower wiring pattern (140)” appears to be in contact with a bottom surface of the lower wiring pattern as seen in FIG. 2 of the Drawings. It is not clear whether the limitation should read “a bottom/lower surface” as the limitations “the first upper wiring pattern” and “lower wiring pattern” are in a vertical relationship or the limitation “covering” merely suggests overlapping. Thus, the limitation renders the claims indefinite and clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 8-10 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2009/0315156 A1 to Harper (“Harper”). As to claim 1, Harper discloses a chip-on-film package comprising: a film substrate (top 608) having a chip mounting region (at 108), an inner lead bonding region (at 112) arranged within the chip mounting region (at 108), and an outer lead bonding region (outside 108) spaced apart from the inner lead bonding region (at 112) in a first direction, and providing upper and lower surfaces opposite to each other; a first upper wiring pattern (112, 114, 116, 124, 128) arranged on the upper surface of the film substrate (top 608) and extending in the first direction from the inner lead bonding region (at 112) to the outer lead bonding region (outside 108); a second upper wiring pattern (614) spaced apart from the first upper wiring pattern (112, 114, 116, 124, 128) in the first direction; a first wiring via (612 under 114) connected to the first upper wiring pattern (112, 114, 116, 124, 128), penetrating the film substrate (top 608) and extending toward the lower surface of the film substrate (top 608); a lower wiring pattern (610) connected to the first wiring via (612 under 114) on the lower surface of the film substrate (top 608), and extending in the first direction; a second wiring via (612 under 614) connected to the second upper wiring pattern (614), penetrating the film substrate (top 608), extending toward the lower surface of the film substrate (top 608), and connected to the lower wiring pattern (610); an upper solder resist layer (126) covering an upper surface of the first upper wiring pattern (112, 114, 116, 124, 128); and a lower solder resist layer (bottom 608) covering an upper surface of the lower wiring pattern (610), wherein an upper surface of the second upper wiring pattern (614) is exposed without being covered by the upper solder resist layer (126) (See Fig. 1, Fig. 6, ¶ 0014-¶ 0018, ¶ 0032, ¶ 0034) (Notes: the limitation “wiring pattern” is interpreted as elements providing signal connections and the limitation “solder resist layer” is interpreted as a layer that prevents further formation of solder. Further, the limitation “region” is defined as an extensive, continuous part of a surface, space, or body by Dictionary.com). As to claim 2, Harper further discloses wherein the lower solder resist layer (bottom 608) completely covers the upper and side surfaces of the lower wiring pattern (610) (See Fig. 6). As to claim 3, Harper further discloses wherein a width (vertical width of 124, 128) of the first upper wiring pattern (112, 114, 116, 124, 128) in a second direction (vertical) perpendicular to the first direction is greater than a width (vertical width of 614) of the second upper wiring pattern (614) in the second direction (vertical) (See Fig. 6). As to claim 8, Harper further discloses wherein a lower surface of the first upper wiring pattern (112, 114, 116, 124, 128) is located at the same vertical level as a lower surface of the second upper wiring pattern (614) (See Fig. 6). As to claim 9, Harper discloses further comprising: a semiconductor chip (108) arranged in the chip mounting region (at 108) of the film substrate (top 608), wherein a part of the first upper wiring pattern (112, 114, 116, 124, 128) overlaps the semiconductor chip (108) in a vertical direction (See Fig. 6). As to claim 10, Harper further discloses wherein the first wiring via (612 under 114) overlaps the upper solder resist layer (126) and the lower solder resist layer (bottom 608) in a vertical direction (See Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0315156 A1 to Harper (“Harper”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2010/0327383 A1 to Hayasaki et al. (“Hayasaki”). The teaching of Harper has been discussed above. As to claim 4, although Harper discloses wherein the first wiring via (612 under 114) has a diameter (See Fig. 6), Harper does not further disclose the diameter that gradually reduces from the lower surface of the film substrate toward the upper surface of the film substrate. However, Hayasaki does disclose the diameter (at 42) that gradually reduces from the lower surface of the film substrate (10) toward the upper surface of the film substrate (10) (See Fig. 2, Fig. 7, Fig. 11, ¶ 0034, ¶ 0045, ¶ 0055, ¶ 0060, ¶ 0061). In view of the teaching of Hayasaki, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Harper to have the diameter that gradually reduces from the lower surface of the film substrate toward the upper surface of the film substrate because the first wiring via is formed without forming a void to improve the reliability (See ¶ 0045, ¶ 0061). As to claim 5, although Harper discloses wherein the lower wiring pattern (610) (See Fig. 6), Harper does not further disclose wherein a first dimple having a first depth is formed on a surface of the lower wiring pattern. However, Hayasaki does disclose wherein a first dimple (deep recess) having a first depth is formed on a surface of the lower wiring pattern (37 bottom) (See Fig. 2, Fig. 7, Fig. 11, ¶ 0034, ¶ 0045, ¶ 0055, ¶ 0060, ¶ 0061). In view of the teaching of Hayasaki, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Harper to have wherein a first dimple having a first depth is formed on a surface of the lower wiring pattern because the first wiring via connected to the lower wiring pattern is formed without forming a void to improve the reliability (See ¶ 0045, ¶ 0061). As to claim 6, Harper in view of Hayasaki discloses wherein a second dimple (ripple top) having a second depth less than the first depth is formed on a surface of the first upper wiring pattern (112, 114, 116, 124, 128/37 top) (See Harper Fig. 6 and Hayasaki Fig. 2).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0315156 A1 to Harper (“Harper”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2021/0125566 A1 to Yang et al. (“Yang”). The teaching of Harper has been discussed above. As to claim 7, although Harper discloses a length of the second upper wiring pattern (614) in the first direction (See Fig. 6), Harper does not further disclose wherein the length is about 500 micrometers to about 1000 micrometers. However, Yang does disclose wherein the length is about 500 micrometers to about 1000 micrometers (See ¶ 0117). In view of the teaching of Yang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Harper to have wherein the length is about 500 micrometers to about 1000 micrometers because the length is adjusted and determined by the overall device dimension and connection requirements and constraints (See ¶ 0117). Further, the applicant also has not established the critical nature of the “wherein the length is about 500 micrometers to about 1000 micrometers”. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to adjust the length in view of design requirements and constraints. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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