Prosecution Insights
Last updated: October 16, 2026
Application No. 18/612,936

APPARATUS

Non-Final OA §103
Filed
Mar 21, 2024
Priority
Mar 28, 2023 — JP 2023-051698
Examiner
GRAY, AARON J
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Canon Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
429 granted / 521 resolved
+14.3% vs TC avg
Strong +30% interview lift
Without
With
+29.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
34 currently pending
Career history
556
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.1%
+13.1% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 521 resolved cases

Office Action

§103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention I and Species II in the reply filed on 09/17/2026 is acknowledged. The traversal is on the ground(s) that claim 1 constitutes a generic claim that encompasses Species II-IV and so supports examination of claims under the generic claim. This is not found persuasive because although examiner agrees with the conclusion that claim 1 is generic to Species II-IV, Claim I is currently rejected as discussed below and the reason for restriction presented in the Restriction still hold so that claims to Species III-IV are currently restricted. Examiner does however note that claims that require all the limitations of a generic claim that is ultimately found allowable will be considered for rejoinder. The requirement is still deemed proper and is therefore made FINAL. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: IMAGING APPARATUS WIRING LAYER. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et. Al. (US 20190181177 A1 hereinafter Kobayashi) and further in view of Yang et. Al. (US 20220173138 A1). Regarding claim 1, Kobayashi teaches in Figs. 20-23 with associated text an apparatus comprising: a plurality of pixels (group of 2 or more adjacent units 21); a layer (substrate including 34, 39 and everything therein (Fig. 20-22, [0183]) a first surface (upper surface) and a second surface (lower surface) opposite the first surface, wherein the layer includes a plurality of photodiodes (structures between isolations 39) (Fig. 20-22, [0182]); and a wiring layer 23M disposed on a first surface side (Fig. 20 and 23, [0187]), wherein the wiring layer includes first wiring 63M1 and second wiring 52M1 (Fig. 20 and 23, [0187]), and wherein a width of the first wiring (first width) disposed between the second wiring of the first photodiode and the second wiring of the second photodiode is greater than a width of the first wiring (second width) disposed between the plurality of pixels in the first direction (see annotated Fig. below). Kobayashi does not specify each of the plurality of pixels includes a first photodiode, a second photodiode located adjacent to the first photodiode 13 in a first direction, and a microlens disposed on a second surface side so as to be common to the first photodiode and the second photodiode, Yang discloses in Figs. 1-2A and 16 with associated text each of a plurality of pixels includes a first photodiode (13 of B4 for example), a second photodiode (13 of A5 for example) located adjacent to the first photodiode in a first direction, and a microlens 31 disposed on a second surface side so as to be common to the first photodiode and the second photodiode (Figs. 1 and 2A, [0063] and [0075]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the microlens and photodiode arrangement of Yang in the apparatus of Kobayashi because according to Yang by using such an arrangement the incident light will be stronger on the center than on the periphery of the pixel array PA due to the (converging) light-adjusting structure 31. For pixel uniformity, the aperture ratio of each pixel may be modified to improve the pixel uniformity [0078]). PNG media_image1.png 744 600 media_image1.png Greyscale Regarding claim 2, Kobayashi teaches the first wiring provides a voltage to one of terminals of the photodiode, and the second wiring provides a voltage to the other terminal ([0185] and [0186]). Regarding claim 3, Kobayashi teaches the first photodiode includes a first region (32a and 32) of a first conductivity type and a second region (33 through 34) of a second conductivity type configured to form PN junction with the first region (Figs. 20-22, [0118]) in this order from the first surface side, and wherein the second wiring of the first photodiode overlaps the first region of the first photodiode in plan view (Fig. 20). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AARON J GRAY/Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Mar 21, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12765104
SEMICONDUCTOR DEVICE WITH RESISTOR AND METHOD FOR MANUFACTURING SAME
3y 10m to grant Granted Oct 13, 2026
Patent 12765132
DISPLAY APPARATUS COMPRISING QUANTUM DOT LAYER WITH RED, BLUE AND GREEN QUANTUM DOTS AND LIGHT EMITTING DIODES WITH A REFECTIVE LAYER
3y 10m to grant Granted Oct 13, 2026
Patent 12757389
SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FUSE STRUCTURE EMBEDDED IN SUBSTRATE
3y 3m to grant Granted Oct 06, 2026
Patent 12745466
Fin Field-Effect Transistor, ESD Protection Circuit, Filter Circuit, and Electronic Device
3y 6m to grant Granted Sep 22, 2026
Patent 12740331
JOSEPHSON JUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 6m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+29.8%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 521 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month