Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The applicant has amended their application as follows:
Amended: 1-4, 6, 8-9, 12-13, 16-17 and 20
Cancelled: 18
Added: 21
Therefore, claims 1-17 and 18-21 are currently pending in the instant application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2024/0221590 A1, hereinafter “Wang”).
As to claim 1, Wang discloses a display device (Fig. 1) comprising:
a first subpixel circuit (Fig. 6 element R) and a second subpixel circuit (G) being disposed adjacent to each other in a first direction, the first subpixel circuit (Fig. 3) and the second subpixel circuit (Fig. 4) each comprising a driving transistor (T3) and a first capacitor (C1);
a first light-emitting diode (Fig. 3 element L) electrically connected to the first subpixel circuit;
a second light-emitting diode (Fig. 4 element L) electrically connected to the second subpixel circuit;
a first signal line (Fig. 6 element GA) extending in the first direction;
a first horizontal voltage line (VIN2) extending in the first direction;
a first transistor (Fig. 3 element T7) of the first subpixel circuit, the first transistor electrically connected to a subpixel electrode of the first light-emitting diode (L) and comprising a gate electrode connected to the first signal line (GA) and a semiconductor layer connected to the first horizontal voltage line (VIN2);
a second horizontal voltage line (Fig. 6 element Vin1) extending in the first direction; and
a second transistor (Fig. 4 element T7) of the second subpixel circuit, the second transistor electrically connected to a subpixel electrode of the second light-emitting diode (L) and comprising a gate electrode connected to the first signal line (GA) and a semiconductor layer connected to the second horizontal voltage line (VIN1),
wherein the first horizontal voltage line and the second horizontal voltage line are disposed in different layers (Para. 0076-0077).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 2021/0391407 A1, hereinafter “Yoon”) in view of Wang et al. (US 2024/0221590 A1, hereinafter “Wang”).
As to claim 1, Yoon (Fig. 1) discloses a display device (1) comprising:
a first subpixel circuit (Pa) and a second subpixel circuit (adjacent Pa) disposed adjacent to each other in a first direction (x-direction), the first subpixel circuit and the second subpixel circuit (Fig. 8) each comprising a driving transistor (T1) and a first capacitor (Cst);
a first light-emitting diode (OLED) electrically connected to the first subpixel circuit;
a second light-emitting diode (OLED, for adjacent pixel) electrically connected to the second subpixel circuit;
a first signal line (Fig. 6 element SS4) extending in the first direction (Fig. 1 element SL; scan lines);
a first horizontal voltage line (Fig. 10 element VL1b) extending in the first direction (Para. 0208);
a first transistor (Fig. 8 element T7) of the first subpixel circuit, the first transistor electrically connected to a subpixel electrode of the first light-emitting diode (OLED) and comprising a gate electrode connected to the first signal line (SS4) and a semiconductor layer connected to the first horizontal voltage line (Vint2);
a second transistor (Fig. 8 element T7) of the second subpixel circuit (for second adjacent pixel), the second transistor electrically connected to a subpixel electrode of the second light-emitting diode (OLED) and comprising a gate electrode connected to the first signal line (SS4) and a semiconductor layer connected to the first horizontal voltage line (VL1b).
Yoon does not disclose a second horizontal voltage line extending in the first direction;
a second transistor (Fig. 8 element T7) of the second subpixel circuit (for second adjacent pixel), the second transistor electrically connected to a subpixel electrode of the second light-emitting diode (OLED) and comprising a gate electrode connected to the first signal line (SS4) and a semiconductor layer connected to the second horizontal voltage line; and
wherein the first horizontal line and the second horizontal voltage line are disposed on different layer.
However, Wang teaches a second horizontal voltage line (Fig. 6 element Vin1) extending in the first direction; and
a second transistor (Fig. 4 element T7) of the second subpixel circuit, the second transistor electrically connected to a subpixel electrode of the second light-emitting diode (L) and comprising a gate electrode connected to the first signal line (GA) and a semiconductor layer connected to the second horizontal voltage line (VIN1),
wherein the first horizontal voltage line and the second horizontal voltage line are disposed in different layers (Para. 0076-0077).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Wang to have different initialization voltages for pixels in the device disclosed by Yoon. The motivation would have been to solve the problem of purple defect (Wang; para. 0072).
As to claim 2, Yoon in view of Wang disclose the display device of claim 1, further comprising: an insulating layer (Yoon; Fig. 16 element 114) interposed between the first horizontal voltage line (VL1b) and the second horizontal voltage line (VL2b), wherein the first horizontal voltage line (VL1b) is disposed under the insulating layer (114), and the second horizontal voltage line (VL2b) is disposed over the insulating layer (114; Para. 0134), and
wherein the second horizontal voltage line overlaps the first horizontal voltage line (Wang; Fig. 6 element VIN1 and VIN2).
As to claim 3, Yoon (Fig. 8) discloses the display device of claim 1, wherein:
each of the first subpixel circuit and the second subpixel circuit further comprises a second capacitor (Cbt),
the first capacitor (Cst) comprises a first lower electrode (CE1) disposed in a same layer (112) as a gate electrode (Fig 11 element G1) of the driving transistor (Para. 0142) and a first upper electrode (CE2) disposed over the first lower electrode (CE1),
the second capacitor (Cbt) comprises a second lower electrode (CE3) disposed in a same layer (112) as the first upper electrode (CE1) and a second upper electrode (CE4) disposed over the second lower electrode (CE2), and
the first horizontal voltage line (VL1b) is disposed in a same layer (113) as the second upper electrode (CE2).
As to claim 4, Yoon (Fig. 11) discloses the display device of claim 3, wherein:
the second lower electrode (CE3) is disposed in a same layer (112) as the first upper electrode (CE1), and
the first lower electrode (CE1) is disposed in a same layer (112) as the gate electrode (G1) of the driving transistor (T1).
As to claim 5, Yoon (Fig. 11) discloses the display device of claim 1, wherein the first horizontal voltage line (VL1b) is electrically connected to the semiconductor layer (S4) of the first transistor (T4) through a bridge electrode (VL1ap; Para. .
As to claim 6, Yoon (Fig. 11) discloses the display device of claim 5, wherein the bridge electrode (VL1ap) is disposed in a same layer (116) as the second horizontal voltage line (VL2b).
As to claim 7, Yoon (Fig. 10) discloses the display device of claim 1, wherein the first signal line (SL3) comprises:
a first sub-signal line (145); and
a second sub-signal line (165) disposed on the first sub-signal line and electrically connected to the first sub-signal line (Para. 0226).
As to claim 8, Yoon (Fig. 10) discloses the display device of claim 7, wherein:
the second sub-signal line (165) is disposed in a same layer (115) as the second horizontal voltage line (VL2b; Para. 0225), and
the first sub-signal line (145) comprises each of the gate electrode of the first transistor (T4) of the first subpixel circuit and the gate electrode of the second transistor of the second subpixel circuit (Para. 0228).
As to claim 9, Yoon (Fig. 11) discloses the display device of claim 1, wherein:
the first transistor (T4) of the first subpixel circuit electrically connects the first horizontal voltage line (VL1b) to the subpixel electrode of the first light-emitting diode (OLED, electrically connects), in response to a signal from the first signal line (Fig. 8 element SL3; T7 directly connects to the OLED), and
the second transistor (T4 of the second pixel) of the second subpixel circuit electrically connects the second horizontal voltage line to the subpixel electrode of the second light-emitting diode, in response to a signal from the first signal line (Para. 0228).
As to claim 10, Yoon (Fig. 17) discloses the display device of claim 1, further comprising:
a plurality of vertical voltage lines (VL1a, VL2a) extending in a second direction (y-direction) crossing the first direction (x-direction),
wherein the plurality of vertical voltage lines (VL1a, VL2a) are disposed apart from one another and a plurality of subpixel circuits (PCA) are arranged between two adjacent vertical voltage lines (VL2a, VL1a).
As to claim 11, Yoon (Fig. 17) discloses the display device of claim 10, further comprising:
a third horizontal voltage line (BML) extending in the first direction (x-direction); and
a third vertical voltage line (BW) extending in the second direction (y-direction),
wherein a portion of a first vertical voltage line (BW) of the plurality of vertical voltage lines comprises a first pattern portion (base portion) having a width greater than a width of another portion of the first vertical voltage line (the body portion) and is electrically connected to the third horizontal voltage line (BML) through a contact hole (BCNT) which is disposed directly under the first pattern portion (base portion; Para. 0130), and
a portion of at a second vertical voltage line (175’) of the plurality of vertical voltage lines comprises a second pattern portion (top portion) having a width greater than a width of another portion of the second vertical voltage line (body portion) and a contact hole (43) which is not directly located under the second pattern portion (top portion of 175’; Para. 0270).
As to claim 12, Yoon (Fig. 15) discloses the display device of claim 11, wherein
with reference to a virtual line (Fig. 11 element 111, line over Cst) extending in the first direction to cross the first capacitor (Cst) in a plan view (Para. 0137), the third horizontal voltage line (BML) is disposed opposite to the first horizontal voltage line (VL1b) and the second horizontal voltage line (Fig. 12 element VL2b, VL1b, VL2b are above the virtual line drawn over 111, Cst).
As to claim 13, Yoon (Fig. 1) discloses a display device (1) comprising:
a first subpixel circuit (Pa) and a second subpixel circuit (adjacent Pa) disposed adjacent to each other in a first direction (x-direction), the first subpixel circuit and the second subpixel circuit (Fig. 8) each comprising a driving transistor (T1) and a first capacitor (Cst);
a first light-emitting diode (OLED) electrically connected to the first subpixel circuit;
a second light-emitting diode (OLED, for adjacent pixel) electrically connected to the second subpixel circuit;
a first signal line (Fig. 6 element SS4) extending in the first direction (Fig. 1 element SL; scan lines);
a second horizontal voltage line (Fig. 14 element VL2b) extending in the first direction (Para. 0208);
a first transistor (Fig. 8 element T7) of the first subpixel circuit, the first transistor electrically connected to a subpixel electrode of the first light-emitting diode (OLED) and comprising a gate electrode connected to the first signal line (SS4) and a semiconductor layer connected to the second horizontal voltage line (Vint2; Fig. 14 element VL2b; Para. 0194);
a second transistor (Fig. 8 element T7) of the second subpixel circuit (for second adjacent pixel), the second transistor electrically connected to a subpixel electrode of the second light-emitting diode (OLED) and comprising a gate electrode connected to the first signal line (SS4) and a semiconductor layer connected to the second horizontal voltage line (VL2b);
a second vertical voltage line (Fig. 17 element 175’) extending in the second direction and electrically connected to the second horizontal voltage line (VL2b).
Yoon does not disclose a first horizontal voltage line extending in the first direction;
a first transistor (Fig. 8 element T7) of the first subpixel circuit, the first transistor electrically connected to a subpixel electrode of the first light-emitting diode (OLED) and comprising a gate electrode connected to the first signal line (SS4) and a semiconductor layer connected to the first horizontal voltage line.
However, Wang teaches a second horizontal voltage line (Fig. 6 element Vin2) extending in the first direction; and
a first transistor (Fig. 4 element T7) of the first subpixel circuit, the first transistor electrically connected to a subpixel electrode of the first light-emitting diode (L) and comprising a gate electrode connected to the first signal line (GA) and a semiconductor layer connected to the first horizontal voltage line (VIN2).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Wang to have different initialization voltages for pixels in the device disclosed by Yoon. The motivation would have been to solve the problem of purple defect (Wang; para. 0072).
As to claim 14, Yoon (Fig. 17) discloses the display device of claim 13, wherein a plurality of subpixel circuits (PCA) are arranged between the first vertical voltage line (VL1a) and the second vertical voltage line (VL2a).
As to claim 15, Yoon (Fig. 17) discloses the display device of claim 13, further comprising:
a third horizontal voltage line (BML) extending in the first direction (x-direction); and
a third vertical voltage line (BW) extending in the second direction (y-direction),
wherein a portion of the third vertical voltage line comprises a first pattern portion (base portion) having a width greater than a width of another portion of the third vertical voltage line (the body portion) and the portion of the third vertical voltage line (BW) is electrically connected to the third horizontal voltage line (BML) through a contact hole (BCNT) which is disposed directly under the first pattern portion (base portion; Para. 0130), and
a portion of at least one selected from among the first vertical voltage line and the second vertical voltage line (175’) comprises a second pattern portion (top portion) having a width greater than a width of another portion of the at least one selected from among the first vertical voltage line and the second vertical voltage line (body portion) and a contact hole (43) which is not directly located under the second pattern portion (top portion of 175’; Para. 0270).
As to claim 16, Yoon (Fig. 8) discloses the display device of claim 13, wherein:
each of the first subpixel circuit and the second subpixel circuit further comprises a second capacitor (Cbt),
the first capacitor (Cst) comprises a first lower electrode (CE1) disposed in a same layer (112) as a gate electrode (Fig 11 element G1) of the driving transistor (Para. 0142) and a first upper electrode (CE2) disposed over the first lower electrode (CE1),
the second capacitor (Cbt) comprises a second lower electrode (CE3) disposed in a same layer (112) as the first upper electrode (CE1) and a second upper electrode (CE4) disposed over the second lower electrode (CE2), and
the first horizontal voltage line (VL1b) is disposed in a same layer (113) as the second upper electrode (CE2) and the second horizontal voltage line (Fig. 12 element VL2b) is disposed in a layer (115) which is different from a layer (113) on which the first horizontal voltage line (VL1b) is disposed.
As to claim 17, Yoon (Fig. 11) discloses the display device of claim 13, wherein the first horizontal voltage line (VL1b) is electrically connected to a semiconductor layer (S4) of the first transistor (T4) through a bridge electrode (VL1ap), and
wherein the bridge electrode (VL1ap) is disposed in a same layer (116) as the second horizontal voltage line (Fig. 16 element VL2b is disposed on 116)
As to claim 19, Yoon (Fig. 10) discloses the display device of claim 13, wherein the first signal line (SL3) comprises:
a first sub-signal line (145); and
a second sub-signal line (165) disposed on the first sub-signal line and electrically connected to the first sub-signal line (Para. 0226).
As to claim 20, Yoon (Fig. 10) discloses the display device of claim 19, wherein:
the second sub-signal line (165) is disposed in a same layer (115) as the second horizontal voltage line (VL2b; Para. 0225), and
the first sub-signal line (145) comprises each of the gate electrode of the first transistor (T4) and the gate electrode of the second transistor (Para. 0228).
As to claim 21, Yoon in view of Wang disclose the display device of claim 13. Wang further teaches wherein the first horizontal voltage line and the second horizontal voltage line are disposed in different layers (Para. 0076-0077), and the second horizontal voltage line overlaps the first horizontal voltage line (Wang; Fig. 6 element VIN1 and VIN2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Lee et al. (US 2021/0098551 A1) discloses two horizontal repair lines (Fig. 4).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPIN GYAWALI whose telephone number is (571)272-1597. The examiner can normally be reached M-F 8:00-4:30 PM.
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BIPIN GYAWALI
Primary Examiner
Art Unit 2625
/BIPIN GYAWALI/Primary Examiner, Art Unit 2625
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