DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8-11, 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yi et al. (US 2018/0366478 A1 hereinafter referred to as “Yi”).
With respect to claim 1, Yi discloses, in Figs.1-12, a non-volatile memory device (see Par.[0018] wherein FIG. 1 to FIG. 10 are schematic, cross-sectional diagrams showing a method for fabricating a nonvolatile memory cell), comprising at least one memory cell, wherein the at least one memory cell comprises: a substrate (10); a trench (105) disposed in the substrate (10) (see Par.[0028]-[0029] wherein an anisotropic dry etching process is carried out to etch the exposed insulating layer 110 and the substrate 10, thereby forming a recessed region 105 in the substrate 10 adjacent to the floating gates 120a and 120b); an erase gate (63) disposed in the trench (105), wherein the erase gate (63) comprises a concave corner (510a) (see Par.[0035]-[0039] wherein as shown in FIG. 9, an etching back process is then performed to etch the remaining polysilicon layer 620, thereby forming an erase gate 63 in and on the recessed region 105; see Par.[0031] wherein a step structure 510a include erase gate 63/620 concave side area towards left and right); a control gate (11) disposed on the substrate (10), wherein a bottom surface of the control gate (11-12) is higher than a bottom surface of the erase gate (63) (see Par.[0019]-[0020], [0035] wherein the erase gate 63 is insulated from the control gates 11 and 12 with oxide-nitride spacers 310b′ and the tunnel dielectric layer 610 disposed above the protruding end portion 121a and 121b of the floating gates 120a and 120b, respectively); and a floating gate (120a, 120b) disposed on the substrate (10), wherein the floating gate (120) comprises a lower tip (121a) pointing toward the concave corner (510a) of the erase gate (63), and the lower tip extending beyond a sidewall of the trench (105) (see Par.[0025]-[0026] wherein as shown in FIG. 3, a self-aligned dry etching process is then performed to etch the exposed polysilicon layer 120, thereby forming the floating gates 120a and 120b directly under the control gates 11 and 12, respectively; see Fig.8 wherein lower tip of floating gate 120 point toward concave side area 510a of erase gate 63 and passed side surface of trench 105; the floating gates 120a and 120b have protruding end portions 121a and 121b, respectively, which are situated directly under the spacers 310b; the protruding end portions 121a and 121b protrude beyond vertical sidewalls of the control gates 11 and 12, respectively).
With respect to claim 2, Yi discloses, in Figs.1-12, the non-volatile memory device, wherein a bottom surface of the floating gate (120) is higher than a bottom surface of the erase gate (63) (see Fig.8).
With respect to claim 5, Yi discloses, in Figs.1-12, the non-volatile memory device, wherein the lower tip is disposed over the trench (see Fig.10).
With respect to claim 8, Yi discloses, in Figs.1-12, the non-volatile memory device, further comprising an erase gate dielectric layer (610) disposed between the lower tip (121) and the erase gate (63) (see Par.[0032] wherein a tunnel dielectric layer 610 is conformally deposited over the stacked gate structures 21, 22, over the substrate 10, and in the recessed region 105; see Par.[0025]-[0026] wherein as shown in FIG. 3, a self-aligned dry etching process is then performed to etch the exposed polysilicon layer 120, thereby forming the floating gates 120a and 120b directly under the control gates 11 and 12, respectively; see Fig.8 wherein lower tip of floating gate 120 point toward concave side area 510a of erase gate 63 and passed side surface of trench 105; the floating gates 120a and 120b have protruding end portions 121a and 121b, respectively, which are situated directly under the spacers 310b; the protruding end portions 121a and 121b protrude beyond vertical sidewalls of the control gates 11 and 12, respectively).
With respect to claim 9, Yi discloses, in Figs.1-12, the non-volatile memory device, wherein the erase gate dielectric layer conformally covers the lower tip, and the erase gate dielectric layer is in direct contact with a bottom surface of the lower tip (see Par.[0032] wherein a tunnel dielectric layer 610 is conformally deposited over the stacked gate structures 21, 22, over the substrate 10, and in the recessed region 105; see Par.[0025]-[0026] wherein as shown in FIG. 3, a self-aligned dry etching process is then performed to etch the exposed polysilicon layer 120, thereby forming the floating gates 120a and 120b directly under the control gates 11 and 12, respectively; see Fig.8 wherein lower tip of floating gate 120 point toward concave side area 510a of erase gate 63 and passed side surface of trench 105; the floating gates 120a and 120b have protruding end portions 121a and 121b, respectively, which are situated directly under the spacers 310b; the protruding end portions 121a and 121b protrude beyond vertical sidewalls of the control gates 11 and 12, respectively).
With respect to claim 10, Yi discloses, in Figs.1-12, the non-volatile memory device, wherein the erase gate dielectric layer is further disposed on a sidewall and bottom surface of the trench (see Par.[0032] wherein a tunnel dielectric layer 610 is conformally deposited over the stacked gate structures 21, 22, over the substrate 10, and in the recessed region 105; see Par.[0025]-[0026] wherein as shown in FIG. 3, a self-aligned dry etching process is then performed to etch the exposed polysilicon layer 120, thereby forming the floating gates 120a and 120b directly under the control gates 11 and 12, respectively; see Fig.8 wherein lower tip of floating gate 120 point toward concave side area 510a of erase gate 63 and passed side surface of trench 105; the floating gates 120a and 120b have protruding end portions 121a and 121b, respectively, which are situated directly under the spacers 310b; the protruding end portions 121a and 121b protrude beyond vertical sidewalls of the control gates 11 and 12, respectively).
With respect to claim 11, Yi discloses, in Figs.1-12, the non-volatile memory device of claim 8, further comprising a floating gate dielectric layer (110) disposed between the floating gate (120) and the substrate (10), wherein an end of the floating gate dielectric layer (110) is in direct contact with the erase gate dielectric layer (610) (see Par.[0019] wherein an insulating layer 110 and a polysilicon layer 120 are deposited over the major surface 10a of the substrate 10 in a blanket manner).
With respect to claim 15, Yi discloses, in Figs.1-12, the non-volatile memory device, further comprising a select gate (62) laterally spaced apart from the erase gate (63) (see Par.[0036]-[0037] wherein as shown in FIG. 10, a lithographic process and an etching process are performed to pattern the remaining polysilicon layer 620 into select gates 62 and 64 on the stacked gate structures 21 and 22 that is opposite to the erase gate 63).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 15-17, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 2024/0265976 A1) in view of Yi.
With respect to claim 1, Yeh discloses, in Figs.1-13W, a non-volatile memory device, comprising at least one memory cell (see Par.[0024] wherein attention is now directed toward embodiments of an electrically erasable programmable nonvolatile memory cell, sometimes called a NOR memory cell or split-gate NOR memory cell), wherein the at least one memory cell comprises: a substrate (102); a trench (1030) disposed in the substrate (102) (see Par.[0069] wherein a trench mask operation is performed in order to form the trench 1030 in the control/erase gate area); an erase gate (112) disposed in the trench; a control gate (124) disposed on the substrate (102), wherein a bottom surface of the control gate (124) is higher than a bottom surface of the erase gate (122); and a floating gate (150) disposed on the substrate (102), wherein the floating gate (150) comprises a lower tip. However, Wang does not explicitly disclose the erase gate comprises a concave corner; wherein the floating gate comprises a lower tip pointing toward the concave corner of the erase gate, and the lower tip extending beyond a sidewall of the trench.
Yi discloses, in Figs.1-12, a non-volatile memory device (see Par.[0018] wherein FIG. 1 to FIG. 10 are schematic, cross-sectional diagrams showing a method for fabricating a nonvolatile memory cell), comprising at least one memory cell, wherein the at least one memory cell comprises: a substrate (10); a trench (105) disposed in the substrate (10) (see Par.[0028]-[0029] wherein an anisotropic dry etching process is carried out to etch the exposed insulating layer 110 and the substrate 10, thereby forming a recessed region 105 in the substrate 10 adjacent to the floating gates 120a and 120b); an erase gate (63) disposed in the trench (105), wherein the erase gate (63) comprises a concave corner (510a) (see Par.[0035]-[0039] wherein as shown in FIG. 9, an etching back process is then performed to etch the remaining polysilicon layer 620, thereby forming an erase gate 63 in and on the recessed region 105; see Par.[0031] wherein a step structure 510a include erase gate 63/620 concave side area towards left and right); a control gate (11) disposed on the substrate (10), wherein a bottom surface of the control gate (11-12) is higher than a bottom surface of the erase gate (63) (see Par.[0019]-[0020], [0035] wherein the erase gate 63 is insulated from the control gates 11 and 12 with oxide-nitride spacers 310b′ and the tunnel dielectric layer 610 disposed above the protruding end portion 121a and 121b of the floating gates 120a and 120b, respectively); and a floating gate (120a, 120b) disposed on the substrate (10), wherein the floating gate (120) comprises a lower tip pointing toward the concave corner (510a) of the erase gate (63), and the lower tip extending beyond a sidewall of the trench (105) (see Par.[0025]-[0026] wherein As shown in FIG. 3, a self-aligned dry etching process is then performed to etch the exposed polysilicon layer 120, thereby forming the floating gates 120a and 120b directly under the control gates 11 and 12, respectively; see Fig.8 wherein lower tip of floating gate 120 point toward concave side area 510a of erase gate 63 and passed side surface of trench 105).
Yeh and Yi are analogous art because they are all directed to a non-volatile memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Yeh to include Yi because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the erase gate material structure in Yeh by including concave cut area in which extends floating gate tip as taught by Yi in order to utilize A concave step shape in the erase gate’s topography can be engineered to improve performance and reliability such as: enhance tunneling efficiency, reduce charge loss, improve retention, better isolation of non-selected cell, lower power consumption, and improve uniformity and scalability.
With respect to claim 2, Yeh discloses, in Figs.1-13W, the non-volatile memory device, wherein a bottom surface of the floating gate is higher than a bottom surface of the erase gate (see Fig.1).
With respect to claim 3, Yeh discloses, in Figs.1-13W, the non-volatile memory device, wherein a top surface of the floating gate (150) is higher than the top surface a of the erase gate (122) (see Fig.1).
With respect to claim 4, Yeh discloses, in Figs.1-13W, the non-volatile memory device, wherein a top surface of the floating gate is level with a top surface of the control gate (see Fig.1).
With respect to claim 7, Yeh discloses, in Figs.1-13W, the non-volatile memory device, further comprising a source region (104) disposed in the substrate (102), wherein the source region is disposed along a sidewall and bottom surface of the trench (see Par.[0025] wherein memory cell 100 includes a semiconductor substrate 102 having a bit line region 104 (sometimes called a drain region or a source region), a surface region 106 apart from the bit line region in a lateral direction, and a trench region 108a/108b apart from the surface region in the lateral direction, the trench region comprising a bottom portion 108a adjacent to a bottom surface of a trench 109 in the substrate 102, and a sidewall portion 108b adjacent to a sidewall of the trench 109).
With respect to claim 15, Yeh discloses, in Figs.1-13W, the non-volatile memory device, further comprising a select gate (130) laterally spaced apart from the erase gate (122) (see Par.[0057] wherein he deep halo implant 306, in combination with the trench implant 302, controls the punch-thru current of unselected rows (control gate 120 voltage Vcg, word line 130 voltage Vwl) to be at 10 pA or lower).
With respect to claim 16, Yeh discloses, in Figs.1-13W, the non-volatile memory device, wherein a top surface of the select gate (130) is higher than the top surface of the erase gate (122) (see Fig.1).
With respect to claim 17, Yeh discloses, in Figs.1-13W, the non-volatile memory device, wherein a top surface of the select gate, a top surface of the control gate, and a top surface of the floating gate are level with each other (see Fig.1).
With respect to claim 19, Yeh discloses, in Figs.1-13W, the non-volatile memory device, wherein the at least one memory cell comprises a first memory cell region and a second memory cell region, each of the first memory cell region and the second memory cell region comprises the erase gate, the control gate and the floating gate, and the non-volatile memory device 100 further comprises a source region shared by the first memory cell region and the second memory cell region, and the source region and the trench extend along a same direction (see Par.[0025] wherein memory cell 100 includes a semiconductor substrate 102 having a bit line region 104 (sometimes called a drain region or a source region), a surface region 106 apart from the bit line region in a lateral direction, and a trench region 108a/108b apart from the surface region in the lateral direction, the trench region comprising a bottom portion 108a adjacent to a bottom surface of a trench 109 in the substrate 102, and a sidewall portion 108b adjacent to a sidewall of the trench 109).
Claims 1, 6, 12-14, 18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Van Schaijk et al. (US 2008/0203463 A1 hereinafter referred to as “Van Schaijk”).
With respect to claim 1, Van Schaijk discloses, in Figs.2-27, a non-volatile memory device, comprising at least one memory cell (see Par.[0003]-[0006], [0022] wherein non-volatile memories (NVMs) are disclosed including the semiconductor device according to the invention; the NVMs may for example be a flash memory or an EEPROM) wherein the at least one memory cell comprises: a substrate (1); a trench disposed in the substrate; an erase gate (10) disposed in the trench; a control gate (19) disposed on the substrate (1), wherein a bottom surface of the control gate (19) is higher than a bottom surface of the erase gate (10); and a floating gate (16) disposed on the substrate (1) (see Par.[0061]-[0062] wherein a tunnel oxide 13 is grown onto the active area 3 of the substrate 1; the EG layer 5 and the cap layer 6 are removed outside the range of the erase gate mask 9 (FIG. 5) and in that way an erase gate 10 with on top a first cap 11 and a second cap 12 is formed; see Par.[0064]-[0067] wherein on top of the IPD layer 18, a second conductive layer 19, which preferably may be a polysilicon layer and which will further be referred to as the control gate (CG) layer 19, is deposited; the first cap 11, which in this embodiment is an oxide cap, will hereby function as a stopping layer. In that way the floating gate 16 is formed, as illustrated in FIG. 7).
Moreover, regarding the limitation “a trench disposed in the substrate; an erase gate disposed in the trench”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Van Schaijk. Therefore, the said limitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
However, Van Schaijk does not disclose wherein the erase gate comprises a concave corner; wherein the floating gate comprises a lower tip pointing toward the concave corner of the erase gate, and the lower tip extending beyond a sidewall of the trench.
Yi discloses, in Figs.1-12, a non-volatile memory device (see Par.[0018] wherein FIG. 1 to FIG. 10 are schematic, cross-sectional diagrams showing a method for fabricating a nonvolatile memory cell), comprising at least one memory cell, wherein the at least one memory cell comprises: a substrate (10); a trench (105) disposed in the substrate (10) (see Par.[0028]-[0029] wherein an anisotropic dry etching process is carried out to etch the exposed insulating layer 110 and the substrate 10, thereby forming a recessed region 105 in the substrate 10 adjacent to the floating gates 120a and 120b); an erase gate (63) disposed in the trench (105), wherein the erase gate (63) comprises a concave corner (510a) (see Par.[0035]-[0039] wherein as shown in FIG. 9, an etching back process is then performed to etch the remaining polysilicon layer 620, thereby forming an erase gate 63 in and on the recessed region 105; see Par.[0031] wherein a step structure 510a include erase gate 63/620 concave side area towards left and right); a control gate (11) disposed on the substrate (10), wherein a bottom surface of the control gate (11-12) is higher than a bottom surface of the erase gate (63) (see Par.[0019]-[0020], [0035] wherein the erase gate 63 is insulated from the control gates 11 and 12 with oxide-nitride spacers 310b′ and the tunnel dielectric layer 610 disposed above the protruding end portion 121a and 121b of the floating gates 120a and 120b, respectively); and a floating gate (120a, 120b) disposed on the substrate (10), wherein the floating gate (120) comprises a lower tip pointing toward the concave corner (510a) of the erase gate (63), and the lower tip extending beyond a sidewall of the trench (105) (see Par.[0025]-[0026] wherein As shown in FIG. 3, a self-aligned dry etching process is then performed to etch the exposed polysilicon layer 120, thereby forming the floating gates 120a and 120b directly under the control gates 11 and 12, respectively; see Fig.8 wherein lower tip of floating gate 120 point toward concave side area 510a of erase gate 63 and passed side surface of trench 105).
Van Schaijk and Yi are analogous art because they are all directed to a non-volatile memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Van Schaijk to include Yi because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the erase gate material structure in Van Schaijk by including concave cut area in which extends floating gate tip as taught by Yi in order to utilize A concave step shape in the erase gate’s topography can be engineered to improve performance and reliability such as: enhance tunneling efficiency, reduce charge loss, improve retention, better isolation of non-selected cell, lower power consumption, and improve uniformity and scalability.
With respect to claim 3, Van Schaijk discloses, in Figs.2-27, the non-volatile memory device, wherein a top surface of the floating gate (16) is higher than the top surface a of the erase gate (10) (see Fig.8).
With respect to claim 6, Van Schaijk discloses, in Figs.2-27, the non-volatile memory device, further comprising a coupling dielectric layer (18) disposed between the top surface of the erase gate (10) and a bottom surface of the control gate (19) (see Par.[0066]-[0068] wherein a dielectric layer 18 is deposited on top of the complete structure as obtained up to now, which is shown in FIG. 7. This is illustrated in FIG. 8. In the further description, the dielectric layer 18 will be referred to as interpoly-dielectric layer (IPD).
With respect to claim 12, Van Schaijk discloses, in Figs.2-27, the non-volatile memory device, wherein the floating gate further comprises: two first sidewalls each extending along a first direction/(vertical directions); and two second sidewalls opposite each other and arranged along a second direction/(horizontal directions) different from the first direction, wherein the control gate (19) extends along the second direction and covers an upper portion of each of the second sidewalls of the floating gate (see Fig.8).
With respect to claim 13, Van Schaijk discloses, in Figs.2-27, the non-volatile memory device, wherein the erase gate extends along the second direction and covers a lower portion of each of the second sidewalls of the floating gate (see Fig.8).
With respect to claim 14, Van Schaijk discloses, in Figs.2-27, the non-volatile memory device, wherein one of the first sidewalls is a curved sidewall covered with the control gate (see Fig.8).
With respect to claim 18, Van Schaijk discloses, in Figs.2-27, the non-volatile memory device, wherein the floating gate further comprises: a horizontal portion disposed under the control gate and comprising the lower tip; and a vertical portion laterally spaced apart from the control gate, wherein a top surface of the horizontal portion is lower than a top surface of the vertical portion (see Fig.8).
With respect to claim 20, Van Schaijk discloses, in Figs.2-27, the non-volatile memory device, wherein the first memory cell region and the second memory cell region have a mirror image of each other (see Fig.8).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
Prosecution Insights