DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The new title submitted 8/19/2026 is acknowledged and accepted by the Office.
Claim Objections
The objection of Claims 16-17 of the last Office action is withdrawn. Claim 16 has been amended to overcome the objection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9, 12, 16-17; 18; and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 2022/0199733 A1-of record, hereafter Zhang) in view of MATSUEDA et al (US 2022/0028335 A1, hereafter Matsueda).
Re claim 1, Zhang discloses in FIGS. 4 and 6 (with references to FIGS. 1-2) a display panel (AMOLED display panel; [0055]), comprising a display region (10 as in FIGS. 1-2; [0069]) and a virtual pixel region (20 as in FIGS. 1-2; [0069]) around the display region (10), wherein:
the display region (10) includes display sub-pixels (101 as in FIGS. 1-2; [0060] and [0063]), and a plurality of signal transmission lines (31/33 as in FIG. 2; [0063] and [0072]-[0074]) is disposed in the display region (10) for connecting ([0063]) pixel circuits (101);
the display panel (AMOLED display panel) further includes a substrate (100 as in FIGS. 1 and 6; [0059] and [0104]), wherein orthographic projections (2D shadows in FIG. 4) of the plurality of signal transmission lines (31/33) on the substrate (100) overlap with the display region (10) and extend into (at dotted line of 10 in FIG. 4) the virtual pixel region (20);
the virtual pixel region (20) includes virtual sub-pixels (201 as in FIGS. 1-2; [0061] and [0064]) and a plurality of virtual signal lines (32 as in FIG. 2; [0064]) connected ([0070]) to the virtual sub-pixels (201); and
at least a portion (all; [0071]-[0073]) of the plurality of the virtual signal lines (32) is connected ([0070]) to the plurality of signal transmission lines (31/33).
Zhang fails to disclose the virtual pixel region includes virtual sub-pixels disposed on at least two sides of the display region.
However,
Matsueda discloses in FIG. 9 a display panel (OLED display panel; [0106]), comprising: a virtual pixel region (dummy pixel region; [0105]), the virtual pixel region (dummy pixel region) includes virtual sub-pixels (dummy pixel regions 457A/457B; [0105]) disposed on at least two sides (left/right sides) of a display region (451/453; [0105]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Zhang by expanding the virtual pixel region to include virtual sub-pixels disposed on at least two sides of the display region, as disclosed by Matsueda, for deterioration measurement of the virtual sub-pixels, the extent of deterioration of the virtual sub-pixels is fed back for brightness adjustment control for the associated pixels in the display region without interfering with displaying images (Matsueda; [0028]).
Re claim 2, Zhang discloses the display panel according to claim 1, wherein: types of the plurality of signal transmission lines (31/33) include at least one of first power signal lines (VDD; [0063]), second power signal lines, or initialization signal lines.
Re claim 3, Zhang discloses the display panel according to claim 2, wherein: the plurality of virtual signal lines (32) is respectively connected ([0066] and [0072]-[0073]) to signal transmission lines (each 31/33) of a same type (VDD; [0066]) among the plurality of signal transmission lines (31/33).
Re claim 4, Zhang discloses the display panel according to claim 2.
But, fails to disclose in the embodiment of FIG. 4, wherein: the plurality of virtual signal lines is respectively connected to signal transmission lines of different types among the plurality of signal transmission lines.
However, Zhang discloses an alternate embodiment in FIG. 5 wherein the plurality of virtual signal lines (32) is respectively connected to signal transmission lines of different types (data lines; [0020]-[0023] and [0097]-[0100]) among the plurality of signal transmission lines, improving the stability of the signal transmission lines ([0098]).
Re claim 5, Zhang discloses the display panel according to claim 1, further including an anode layer (40; [0104]) on a side (upper plane) of the substrate, wherein: the anode layer (40) includes anodes (dummy anodes; [0032] and [0068]) of the virtual sub-pixels (201); and the anodes (dummy anodes) of at least a portion (all) of the virtual sub-pixels (201) are connected ([0032]; [0066] and [0072]-[0073]) to the first power signal lines (31/33) to receive a first power signal transmitted (positive power; [0066] and [0072]-[0073]) by the first power signal lines (VDD 31/33).
Re claim 6, Zhang discloses the display panel according to claim 5, wherein: the anode (dummy anode) of each virtual sub-pixel (201) is connected (electrically by 34; [0032]; [0085] and [0092]) to each other.
Re claim 9, Zhang discloses the display panel according to claim 1, wherein: the plurality of virtual signal lines (32) and the virtual sub-pixels (201) are located on a same side (upper plane) of the substrate (100), and a width (lateral expanse) of an orthographic projection (2D shadow) of the virtual sub-pixels (201) on the substrate (100) is larger than or equal to (FIG. 7; [0109]) a width (lateral expanse) of an orthographic projection (2D shadow) of the plurality of virtual signal lines (32) on the substrate (100).
Re claim 12, Zhang discloses the display panel according to claim 2, wherein: at least a portion (all) of the virtual sub-pixels (201) is used to receive two types of electric signals (VDD and VSS; [0070] and [0076]).
Re claims 16-17, Zhang discloses the display panel according to claim 1, further including shielding signal lines on a side (upper surface) of the substrate (100), wherein: the shielding signal lines (metals of 31/33 as in 30; [0033] and [0106]-[0107]) are located in the virtual pixel region, and orthographic projections (2D shadows) of the shielding signal lines (metals of 31/33 as in 30) on the substrate (100) overlap (coincide with in FIG. 7; [0109]) orthographic projections (2D shadows) of at least a portion (all) of the virtual sub-pixels (201) on the substrate (100); and the plurality of signal transmission lines (31/33) is connected to (laminated with) the shielding signal lines (metals of 31 as in 30); and wherein: the shielding signal lines (metals of 31/33 as in 30) are disposed around (partially at 300 in FIG. 4) the display region (10).
Re claim 18, Zhang discloses in FIGS. 4 and 6 (with references to FIGS. 1-2) a fabrication method of a display panel (AMOLED display panel; [0055]), comprising:
providing a substrate (100 as in FIGS. 1 and 6; [0059] and [0104]), wherein the substrate (100) includes a first region (core of 100) corresponding to a display region (10 as in FIGS. 1-2; [0069]) of the display panel (AMOLED display panel) and a second region (periphery) corresponding to a virtual pixel region (20 as in FIGS. 1-2; [0069]) of the display panel (AMOLED display panel);
forming a composite dielectric layer (laminate 200/60/80/110; [0104]) on a side (upper surface) of the substrate (100); and
forming signal transmission lines (31/33 as in FIG. 2; [0063] and [0072]-[0074]) and virtual signal lines (32 as in FIG. 2; [0064]) on a side (upper surface at 30; [0033]) of the composite dielectric layer (laminate 200/60/80/110) away from (above) the substrate (100), wherein:
orthographic projections (2D shadows) of the signal transmission lines (31/33) on the substrate (100) overlap (coincide; FIGS. 4 and 7) with the first region (core of 100) and extend to the second region (periphery),
orthographic projections (2D shadows) of the virtual signal lines (32) on the substrate (100) are located (FIGS. 4 and 7) in the second region (periphery);
at least a portion (all) of the virtual signal lines (32) is connected ([0070]) to the signal transmission lines (31/33); and
the signal transmission lines (31/33) include signal lines (VDD; [0063]) for connecting pixel circuits (comprising 50/60/30; [0102]; [0104] and [0113]).
Zhang fails to disclose wherein the second region surrounds the first region on at least two sides.
However, Matsuda discloses left/right dummy pixel regions (457A/457B) which would render these limitations obvious as discussed above for claim 1.
Re claim 20, Zhang discloses in FIGS. 4 and 6 (with references to FIGS. 1-2) a display device (phone, computer, TV, etc.; [0131]), comprising a display panel (AMOLED display panel; [0055]), wherein:
the display panel (AMOLED display panel) includes a display region (10 as in FIGS. 1-2; [0069]) and a virtual pixel region (20 as in FIGS. 1-2; [0069]) around the display region (10):
the display region (10) includes display sub-pixels (101 as in FIGS. 1-2; [0060] and [0063]), and a plurality of signal transmission lines (31/33 as in FIG. 2; [0063] and [0072]) is disposed in the display region (10) for connecting ([0063]) pixel circuits (101);
the display panel (AMOLED display panel) further includes a substrate (100 as in FIGS. 1 and 6; [0059] and [0104]), wherein orthographic projections (2D shadows in FIG. 4) of the plurality of signal transmission lines (31/33) on the substrate (100) overlap with the display region (10) and extend into (at dotted line of 10 in FIG. 4) the virtual pixel region (20);
the virtual pixel region (20) includes virtual sub-pixels (201 as in FIGS. 1-2; [0061] and [0064]) and a plurality of virtual signal lines (32 as in FIG. 2; [0064]) connected ([0070]) to the virtual sub-pixels (201); and
at least a portion (all; [0071]-[0073]) of the plurality of the virtual signal lines (32) is connected ([0070]) to the plurality of signal transmission lines (31/33).
Zhang fails to disclose the virtual pixel region includes virtual sub-pixels disposed on at least two sides of the display region.
However, Matsuda discloses left/right dummy pixel regions (457A/457B) which would render these limitations obvious as discussed above for claim 1.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Matsueda as applied to claim 5 above, and further in view of Yokoyama (US 2004/0130514 A1-of record).
Re claim 7, Zhang discloses the display panel according to claim 5, wherein: the virtual pixel region (20) includes a plurality of irregular-shaped regions (four curved corners).
But, fails to disclose the anode layer (40) includes an irregular-shaped sub-anode layer located in each of the plurality of irregular-shaped regions (four curved corners), and the irregular-shaped sub-anode layer includes an anode of one corresponding virtual sub-pixel in the irregular-shaped region; irregular-shaped sub-anode layers are connected to the first power signal lines and are used to receive the first power signal transmitted by the first power signal lines.
However,
Yokoyama discloses in FIG. 7 a display panel (active type color EL device; [0002]), comprising a plurality of irregular-shaped regions (wavy columns of pixels), and an anode layer (all anodes 7; [0038]) which includes an irregular-shaped sub-anode layer (all 7R/7G/7B) located in each (all) of the plurality of irregular-shaped regions (wavy columns of pixels), and irregular-shaped sub-anode layers (all 7R/7G/7B) are connected to first power signal lines (2; [0032]) and are used to receive a first power signal (drive source COM; [0032]) transmitted by the first power signal lines (2).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Zhang by using the plurality of irregular-shaped regions of Yokoyama, in both the first and second regions of Zhang, to go the irregular-shaped regions of Zhang, such that the anode layer (40) includes an irregular-shaped sub-anode layer located in each of the plurality of irregular-shaped regions (four curved corners), and the irregular-shaped sub-anode layer includes an anode of one corresponding virtual sub-pixel in the irregular-shaped region; irregular-shaped sub-anode layers are connected to the first power signal lines and are used to receive the first power signal transmitted by the first power signal lines, producing a delta pixel arrangement where pixels of different colors adjoin with one another in the column direction, gaps between the sub-pixels in the column direction can be sufficiently secured, capacity against diffusion of the luminescent materials is increased in the vertical direction when forming the respective RGB luminescent layers, thereby reducing a possibility of color mixture even if the luminescent layers are formed with manufacturing accuracy (Yokoyama; [0040]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Matsueda as applied to claim 2 above, and further in view of Kim et al (US 2011/0241563 A1-of record, hereafter Kim).
Re claim 8, Zhang discloses the display panel according to claim 2, further a cathode layer (150; [0032] and [0104]) on a side (upper plane) of the substrate (100), wherein: the cathode layer (150) includes cathodes (dummy cathodes as in dummy anodes) of the virtual sub-pixels (201).
But, fails to disclose the cathodes (each dummy cathode) of at least a portion (all) of the virtual sub-pixels (201) are connected to the second power signal lines to receive a second power signal transmitted by the second power signal lines.
However,
Kim discloses in FIG. 1 a display panel (OLED display; [0024]), comprising cathodes (of 70; [0035]) of at least a portion (all) of the sub-pixels (PE; [0035]) are connected to second power signal lines (each CE; [0036]) to receive a second power signal (driving power line 150; [0036]) transmitted by the second power signal lines (each CE).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Zhang by using the driving power signal and second power signal lines configuration of Kim for the expected result of supplying a second power signal to the display panel, using a bus approach allowing the cathodes (each dummy cathode) of at least a portion (all) of the virtual sub-pixels (201) to be connected to the second power signal lines to receive a second power signal transmitted by the second power signal lines, which permits multiplexing of both the sub-pixels and virtual sub-pixels.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Matsueda as applied to claim 2 above, and further in view of GUAN et al (US 2024/0251598 A1, hereafter Guan).
Re claims 10-11, Zhang discloses the display panel according to claim 2, further including a first metal layer (70; [0104]), a second metal layer (90; [0104]), and a third metal layer (30; [0104]), wherein: the first metal layer (70), the second metal layer (90) and the third metal layer (30) are sequentially away (70/90/30 bottom to top) from the substrate (100) as part of a 7T1C pixel circuit configuration ([0113]).
But, fail to disclose the initialization signal lines are located in the second metal layer; one virtual sub-pixel includes a signal receiving layer, and the signal receiving layer is located in the second metal layer; and signal receiving layers of at least a portion of the virtual sub-pixels are connected to the initialization signal lines to receive an initialization signal transmitted by the initialization signal lines; and
the initialization signal lines are located in the third metal layer; one virtual sub-pixel includes a signal receiving layer, and the signal receiving layer is located in the third metal layer; and signal receiving layers of at least a portion of the virtual sub-pixels are connected to the initialization signal lines to receive an initialization signal transmitted by the initialization signal lines.
However,
Guan discloses in FIG. 6 a display panel (OLED display; [0024]), comprising a 7T1C pixel driving circuit ([0129]), identical to the 7T1C pixel circuit of the instant Specification.
Therefore, it would be obvious, through a “rearrangement of parts” (MPEP 2144.04 § VI. C.), for the 7T1C pixel driving circuit of Guan to be configured as claimed, such that the initialization signal lines are located in the second metal layer; one virtual sub-pixel includes a signal receiving layer, and the signal receiving layer is located in the second metal layer; and signal receiving layers of at least a portion of the virtual sub-pixels are connected to the initialization signal lines to receive an initialization signal transmitted by the initialization signal lines; and the initialization signal lines are located in the third metal layer; one virtual sub-pixel includes a signal receiving layer, and the signal receiving layer is located in the third metal layer; and signal receiving layers of at least a portion of the virtual sub-pixels are connected to the initialization signal lines to receive an initialization signal transmitted by the initialization signal lines, and still operate the display panel of Zhang with improved brightness stability (Zhang; [0066]) and improved voltage stability of the power lines (Zhang; [0067]).
Allowable Subject Matter
Claims 13-15 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 13, the prior art cannot anticipate, or render obvious the limitations of: the plurality of signal transmission lines include second signal transmission sub-lines extending along a second direction; the first signal transmission sub-lines and the second signal transmission sub-lines of the same type are connected; the first signal transmission sub-lines are connected to virtual signal lines extending along the second direction among the plurality of virtual signal lines; the second signal transmission sub-lines are connected to virtual signal lines extending along the first direction among the plurality of virtual signal lines; and the first direction and the second direction intersect, in combination with the additionally claimed features of claims 1-2 and 13.
B. Re claim 14, the prior art cannot anticipate, or render obvious the limitations of: the second signal transmission sub-lines include second power signal sub-lines extending along the second direction, the first power signal sub-lines are connected to the second power signal sub-lines; and the first power signal sub-lines and the second power signal sub-lines are respectively used to transmit one of the first power signal and the second power signal, in combination with the additionally claimed features of claims 1-2 and 13-14.
C. Re claim 15, the prior art cannot anticipate, or render obvious the limitations of: the first signal transmission sub-lines include first initialization signal sub-lines extending along the first direction; the second signal transmission sub-lines include second initialization signal sub-lines extending along the second direction, the first initialization signal sub-lines are connected to the second initialization signal sub-lines; and the first initialization signal sub-lines and the second initialization signal sub-lines are respectively used to transmit initialization signals, in combination with the additionally claimed features of claims 1-2, 13 and 15.
D. Re claim 19, the prior art cannot anticipate, or render obvious the limitations of: the signal transmission lines include second signal transmission sub-lines; and forming the signal transmission lines and virtual signal lines on the side of the composite dielectric layer away from the substrate includes: forming the second signal transmission sub-lines extending along a second direction, wherein: orthographic projections of the first signal transmission sub-lines and the second signal transmission sub-lines on the substrate respectively overlap with the first region and extend to the second region, and the first signal transmission sub-lines and the second signal transmission sub-lines are respectively connected to the virtual signal lines, in combination with the additionally claimed features of claims 18 and 19.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1; 18; and 20 have been considered but are moot because the new ground of rejection relies on a reference combination not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
For the record, the applicant’s argument against first power connection line (33) being part of the plurality of signal transmission lines is not persuasive since Zhang discloses signal lines 31 and 33 are formed in a one-time patterning process ([0074]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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