DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I in the reply filed on 01/23/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention II (method).
Allowable Subject Matter
Claims 4, 5, 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 6, 7, 10 – 12, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2018/0166372; herein referenced as “Shimizu’372”) in view of Shimizu’276 (US 2015/0357276; herein referenced as “Shimizu’276”).
Regarding Claim 1, Shimizu (US 2018/0166372; herein referenced as “Shimizu’372”) discloses a wiring substrate (Fig 21A-23,1), comprising: a core substrate (20) comprising a through-hole conductor (21; [0031]); a first resin insulating layer (61; [0045]) formed on the core substrate (20); a first conductor layer (70) formed on the first resin insulating layer (61) and comprising a seed layer (71) and (electrolytic plating [0111]) layer (74) formed on the seed layer (71); a via conductor (70B) formed in the first resin insulating layer (61) such that the via conductor (70B) electrically connects ([0038]) the through-hole conductor (21) and the first conductor layer (70); and a second resin insulating layer (63) formed on the first resin insulating layer (61) such that the second resin insulating layer (63) is covering the first conductor layer (50), wherein the core substrate (20) includes a glass substrate ([0030] “glass”) such that the through-hole conductor (21) is penetrating through the glass substrate (20), the first conductor layer (70) is formed such that the seed layer (71) includes a first layer (72) formed on a surface of the first resin insulating layer (61) and a second layer (73) formed on the first layer (72), and the first conductor layer (70) includes a conductor circuit (70) such that a width (see 72T) of the first layer (72) is larger than a width of the second layer (73) in the conductor circuit (70).
Shimizu’372 does not disclose that a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit.
Shimizu’276 (US 2015/0357276; herein referenced as “Shimizu’276”) teaches of a wiring substrate (see Fig 2) wherein a (electrolytic plating [0103]) layer (50B) has a width that is greater than a width of a first layer (50A) in the cross section of a conductor circuit (50) in a second conductor layer (50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Shimizu’372, such that a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit as taught by Shimizu’276, in order to provide more easier miniaturization, limit defoliation, and reduce issues potentially from roughening (Shimizu’276, [0005,0099,0123-0127]).
Claim states a “electrolytic plating” but “electrolytic plating” does not represent product structure but only refers to the process by which the layer is formed. Thus Claim is a product claim that recites a process step(s) of plating and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 2, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim and Shimizu’372 further discloses the wiring substrate (Fig 21-23) according to claim 1, wherein the first conductor layer (70) is formed such that a width of the conductor circuit (70) has a minimum value (see Fig 22 showing a width of 71,74) at a boundary portion (portion or region or area where 71 interfaces with 74; note that the claim has not structurally defined this claimed portion) between the seed layer (71) and the (electrolytic) plating layer (74).
Claim states a “electrolytic plating” but “electrolytic plating” does not represent product structure but only refers to the process by which the layer is formed. Thus Claim is a product claim that recites a process step(s) of plating and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claims 6 and 17, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim and Shimizu’372 further discloses the wiring substrate (Fig 23) according to claims 1 and 2, wherein the first conductor layer is formed such that the first layer (72) and the second layer (73) are formed (by sputtering [0050]).
Claim states a “sputtering” but “sputtering” does not represent product structure but only refers to the process by which the layer is formed. Thus Claim is a product claim that recites a process step(s) of sputtering and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claims 7 and 18, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim and Shimizu’372 further discloses the wiring substrate (Fig 23) according to claims 1 and 2, wherein the first conductor layer is formed such that the first layer (72) includes a copper alloy ([0050]) and that the second layer (73) includes copper ([0050]). Please note that in the instant application, page 8 line 8-page 9, line 11, Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 10, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim and Shimizu’372 further discloses the wiring substrate (Fig 23) according to claim 1, wherein the first conductor layer (70) is formed such that the seed layer (71) has a thickness in a range of 0.02 μm to 1.0 μm ([0050,0059]).
Regarding Claim 11, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim and Shimizu’372 further discloses the wiring substrate (Fig 23) according to claim 1, wherein the first conductor layer (70) is formed such that a thickness of the first layer (72) is in a range of 0.01 μm to 0.5 μm ([0050,0059]).
Regarding Claim 12, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim and Shimizu’372 further discloses the wiring substrate (Fig 23) according to claim 1, wherein the first conductor layer (70) is formed such that a thickness of the second layer (73) is in a range of 0.01 μm to 0.9 μm ([0050,0059]).
Claim(s) 3, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2018/0166372; herein referenced as “Shimizu’372”) in view of Shimizu’276 (US 2015/0357276; herein referenced as “Shimizu’276”) as applied to claims 1 and 2 above and further in view of Hwang US 2022/0071016 A1).
Regarding Claims 3 and 14, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim.
Shimizu’372 further discloses the wiring substrate (Fig 21-23) according to claims 1 and 2, wherein the first resin insulating layer (61) includes inorganic particles ([0045]).
Shimizu’372 does not disclose the wiring substrate according to claims 1 and 2, wherein the first resin insulating layer includes inorganic particles and resin such that the inorganic particles include first inorganic particles and second inorganic particles such that the first inorganic particles are forming an inner wall surface in an opening in which the via conductor is formed, that the second inorganic particles are embedded in the first resin insulating layer, and that shapes of the first inorganic particles are different from shapes of the second inorganic particles.
Hwang US 2022/0071016 A1) teaches of a wiring substrate (Fig 13-16), wherein a first resin insulating layer (310) includes inorganic ([0071]) particles (312) and resin (311) such that the inorganic particles (312) include first inorganic particles (312 at VH wall) and second inorganic particles (312 away from VH wall) such that the first inorganic particles (312 shown as a partial sphere or partial circle at the edge or surface of VH1,VH2) are forming an inner wall surface (inner wall of VH) in an opening (VH) in which a via conductor (350; [0137]) is formed, that the second inorganic particles (312 shown as a whole sphere or circle away from VH1) are embedded in the first resin insulating layer (310), and that shapes of the first inorganic particles are different (see Fig 13-16) from shapes of the second inorganic particles.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Shimizu’372 in view of Shimizu’276, wherein the first resin insulating layer includes inorganic particles and resin such that the inorganic particles include first inorganic particles and second inorganic particles such that the first inorganic particles are forming an inner wall surface in an opening in which the via conductor is formed, that the second inorganic particles are embedded in the first resin insulating layer, and that shapes of the first inorganic particles are different from shapes of the second inorganic particles as taught by Hwang, in order to provide a desired roughened surface, improve peel strength, and improve product reliability (Hwang, [0036,0144]).
Regarding Claim 13, Shimizu’372 in view of Shimizu’276 and Hwang teaches the limitations of the preceding claim and Shimizu’372 further discloses the wiring substrate (Fig 21-23) according to claim 3, wherein the first resin insulating layer (61) is formed and comprising the first inorganic particles ([0045]).
Shimizu’372 does not disclose wherein the first resin insulating layer is formed such that the first inorganic particles have flat parts having exposed surfaces and that the inner wall surface in the opening includes the exposed surfaces of the flat parts and a surface of the resin.
Hwang US 2022/0071016 A1) teaches of a wiring substrate (Fig 13-16), wherein a first resin insulating layer (310) includes inorganic ([0071]) particles (312) and resin (311), wherein the first resin insulating layer (310) is formed such that the first inorganic particles (312) have flat parts (flat surfaces of 312 at VH) having exposed surfaces and that the inner wall surface (wall of VH) in an opening (VH) includes the exposed surfaces of the flat parts (flat surfaces of 312 in VH) and a surface (inner wall of 311 at VH) of the resin (311).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Shimizu’372 in view of Shimizu’276 and Hwang, wherein the first resin insulating layer is formed such that the first inorganic particles have flat parts having exposed surfaces and that the inner wall surface in the opening includes the exposed surfaces of the flat parts and a surface of the resin as taught by Hwang, in order to provide a desired roughened surface, improve peel strength, and improve product reliability (Hwang, [0036,0144]).
Claim(s) 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2018/0166372; herein referenced as “Shimizu’372”) in view of Shimizu’276 (US 2015/0357276; herein referenced as “Shimizu’276”) as applied to claims 7 and 18 above and further in view of Ebe (US 2012/0031648 A1).
Regarding Claims 8 and 19, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim.
Shimizu’372 does not disclose the wiring substrate according to claims 7 and 18, wherein the first conductor layer is formed such that a content of the copper in the copper alloy is 90.0 at % or more.
Ebe (US 2012/0031648 A1) teaches of a printed wiring board (Fig 1), wherein the seed layer (2a,2b) includes the first layer (2a) comprising a combination of copper alloys of different materials ([0026]), or a combination of a copper alloy and copper ([0026]), and the second layer (2b) comprising a combination of copper alloys ([0026]) of different materials, or a combination of a copper alloy and copper ([0026]), wherein the first conductor layer is formed such that a content of the copper in the copper alloy is 90.0 at % or more ([0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the board as taught by Shimizu’372 in view of Shimizu’276, wherein the first conductor layer is formed such that a content of the copper in the copper alloy is 90.0 at % or more as taught by Ebe, in order to provide a solid solution strengthening, prevent crystal grain growth and suppress softening (Ebe, [0026]). Please note that in the instant application, page 8 line 8-page 9, line 11, Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2018/0166372; herein referenced as “Shimizu’372”) in view of Shimizu’276 (US 2015/0357276; herein referenced as “Shimizu’276”) as applied to claim 7 above and further in view of Lin (US 2012/0043127 A1).
Regarding Claim 9, Shimizu’372 in view of Shimizu’276 teaches the limitations of the preceding claim.
Shimizu’372 does not disclose the wiring substrate according to claim 7, wherein the first conductor layer is formed such that the copper alloy includes copper, aluminum and at least one metal selected from the group consisting of nickel, zinc, gallium, silicon, and magnesium.
Lin (US 2012/0043127 A1) teaches of a wiring substrate (Fig 3), wherein a conductor layer (220) is formed such that a copper alloy includes copper ([0022]), aluminum ([0022]), and at least one metal selected from the group consisting of nickel ([0022]), zinc, gallium, silicon ([0022]), and magnesium.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Shimizu’372 in view of Shimizu’276, wherein the first conductor layer is formed such that the copper alloy includes copper, aluminum and at least one metal selected from the group consisting of nickel, zinc, gallium, silicon, and magnesium as taught by Lin, in order to facilitates the nucleation and growing of subsequent metal layers formed by the electro plating process (Lin, [0022]) and furthermore since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Please note that in the instant application, page 8 line 8-page 9, line 11, Applicant has not disclosed any criticality for the claimed limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kajita (US 2016/0150642 A1) teaches of a wiring substrate (Fig 1), comprising: a core substrate (7) comprising a through-hole conductor (8; [0029]); a first resin insulating layer (lower 10 above 5; [0034,0044]) formed on the core substrate (7); a first conductor layer (11 on lower 10 above 5) formed on the first resin insulating layer (10) and comprising a seed layer (26,27) and an (electrolytic [0061]) plating layer (28) formed on the seed layer (26,27); a via conductor (12) formed in the first resin insulating layer (10) such that the via conductor (12) electrically connects ([0029-0032]) the through-hole conductor (8) and the first conductor layer (11); and a second resin insulating layer (upper 10 above 5; [0034,0044]) formed on the first resin insulating layer (lower 10 above 5; [0034,0044]) such that the second resin insulating layer (10) is covering the first conductor layer (11), wherein the core substrate (7) includes a glass substrate ([0028] “glass”) such that the through-hole conductor (8) is penetrating through the glass substrate (7), the first conductor layer (11) is formed such that the seed layer (26,27) includes a first layer (26) formed on a surface of the first resin insulating layer (lower 10 above 5) and a second layer (27) formed on the first layer (26). This could be used in a 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896