DETAILED ACTION
This action is responsive to the amendments filed March 12, 2026. Prior to entry, claims 1-20 were pending. Claims 1, 11, and 19 are amended. Claims 12, 17, and 18 are cancelled. Thus, claims 1-11, 13-16, and 19-20 are currently pending. Claims 1, 11, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment canceling claim 12 as a response to the prior 35 U.S.C. § 112(b) rejection is acknowledged and accepted. The rejection is moot.
Claim Objections
Claims 1, 11, and 19 are objected to because of the following minor informalities:
Regarding claim 1, the second line recites the term "unseleted" appears to be a spelling error.
The eleventh line recites the phrase "applying a electron erase verify" contains an improper indefinite article ("a" before a vowel sound). The correct form is "applying an electron erase verify".
Regarding claim 11, the thirteenth line recites the phrase "applying a electron erase verify" contains an improper indefinite article ("a" before a vowel sound). The correct form is "applying an electron erase verify".
The fourth line recites the phrase "the control circuit configured to:" followed by a list of gerunds instead of proper infinitive form ("applying" – should be "apply", "performing" – should be "perform", "determining" – should be "determine").
Regarding claim 19, the tenth line recites the phrase "applying an electron erase verify level to a second selected one of the word lines selected word lines applying a positive bias to unselectd word line to detect slow-to-erase word lines s…". The phrase "selected word lines" appears to be an inadvertent duplicate. The word "unselectd" appears to be misspelled. The single "s" after the word lines appears to be a typographical error.
Appropriate correction is required.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites: "performing a first erase verify test by applying a hole erase verify level to memory cells of the selected word lines and a negative bias to the unselected word lines to detect fast-to-erase word lines to sense a hole conduction current".
The phrase "to detect fast-to-erase word lines to sense a hole conduction current" renders the claim indefinite because it is grammatically and syntactically ambiguous as to the intended function and relationship of the recited "applying" step.
Specifically:
The antecedent and modification ambiguity of the infinitives "to detect... to sense…": The two infinitive phrases are placed immediately after the gerund phrase "by applying a hole erase verify level… and a negative bias…". It is unclear whether:
the "applying" step itself is performed to detect fast-to-erase word lines, and the detection is accomplished by sensing a hole conduction current (i.e., purpose/modifier of the entire verify test), or
the "applying" step is performed to detect fast-to-erase word lines and separately to sense a hole conduction current (i.e., two parallel but unconnected purposes), or
the sensing of hole condition current is itself the act that detects the fast-to-erase word lines. Or
some other relationship exists between the application of the level/bias, detection, and sensing.
Because the claim does not use clear transitional language, punctuation, or structure (e.g., "by applying… in order to detect… by sensing" or "by applying… and sensing… to detect…"), a person of ordinary skill in the art cannot reasonably determine the metes and bounds of the limitation.
Lack of clarity on what performs the detection versus the sensing:The phrase does not specify whether the "hole erase verify level" (applied to the selected word line) or the "negative bias" (applied to unselected word lines) is the element that directly causes the "detect[ion]" or the "sense[ing]". The specification (e.g., [0233]-[0234], [0240]) describes sensing hole conduction current after applying the hole erase verify level and negative bias in order to determine whether the word line passes. However, the claim language does not clearly tie the recited "applying" action to either the detection or the sensing step in a definite manner. This disconnect between the recited means ("applying") and the intended result ("to detect… to sense") renders the functional limitation indefinite.
Because of these defects, it is impossible to ascertain with reasonable certainty whether the claim requires the application of the hole erase very level (and negative bias) for the purpose of detecting fast-to-erase word lines via hole conduction current sensing, or whether the sensing and detection are separate or differently related steps.
Dependent claims 2-10 inherit the deficiency of base claim 1 and are therefore similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-10, 11, 15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al. (US 11335411; “Lien” – of record) in view of Maeda (US 20200402597), and further in view of Wong (US 62855593).
Regarding independent claim 1, notwithstanding the rejection for indefiniteness above, Lien discloses an apparatus comprising:
memory cells coupled to a selected word line and unseleted word lines (col. 9, ln 55-56; " the memory cell is connected to a selected or unselected word line");
and a control circuit coupled to the selected word line, the unselected word lines and the memory cells (Fig. 7: Row decoder 124),
the control circuit configured to perform an erase operation on the memory cells by:
applying an erase pulse to the selected word line (col. 2, ln. 60-63; "performing an erase operation for a set of memory cells, where the erase operation applies a staircase or multi-level word line voltage concurrent with a fixed level erase pulse";
and performing a second erase verify test by applying a electron erase verify level to memory cells of the selected word lines and a positive bias to the unselected word lines to detect slow-to-erase word lines on the memory cell to sense an electron conduction current (col. 3, ln. 49-50; "the erase operation involves multiple erase-verify iterations". See also Fig. 9 which illustrates the application of positive erase verify voltage VvEr. See also col. 18, ln. 25-27 "The erase operation is completed when the Vth of all, or nearly all, of the memory cells is below a verify voltage of VvEr". It is well understood in the art that the standard erase verify operation (e.g., electron erase verify) necessarily sets any unselected memory cells in a given string to a positive voltage. It is noted that the three functions of the control circuit cited to be performed (apply erase pulse, erase verify test 1 and erase verify test 2) are not recited to be conducted in any specific order, sequence, or with any temporal relationship. There is no transitional wording such as "after," "in response to," "subsequently," "following," or "prior to" that would limit the claim to a specific sequence.).
Lien discloses a first and second erase verify test but is silent about the specific type of current-mode sensing used in the erase-verify operation.
However, Maeda teaches performing a first erase verify test by applying a hole erase verify level to memory cells of the selected word lines (para. 174; "the semiconductor memory device 1 according to the first embodiment can execute an erase verify operation in units of the block BLK and an erase verify operation in units of the string unit SU by a read operation using hole conduction.)
Lien and Maeda are silent with respect to applying a negative voltage to the unselected word lines during the first erase verify test.
However, Wong teaches and a negative bias to the unselected word lines to detect fast-to-erase word lines to sense a hole conduction current (col. 6, ln. 45-49; "During a read or verify operation, word-line decoder 120 applies a negative voltage (e.g., approximately -3 volts) to the unselected ones of word lines WL1 to WLM, where the unselected word-lines are the ones that do not contain the memory cell selected for the read or verify operation");
Lien, Maeda, and Wong are from the same field of endeavor as applicant’s invention directed to erase-verify operation in non-volatile memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the erase verify operations of Lien by incorporating the hole conduction erase verify taught by Maeda combined with the negative unselected word line bias taught by Wong. Doing so would improve the efficiency of the erase-verify operation and reliability of the memory device.
Regarding claim 2, Lien, Maeda and Wong combined disclose the limitations of claim 1.
As applied, Lien further discloses wherein performing the first erase verify test comprises
applying a first erase verify level to the word line (Fig. 12:S1205 where the step performs an erase verify),
Regarding claim 4, Lien Maeda and Wong combined disclose the limitations of claim 1.
As applied, Maeda further discloses wherein the control circuit is further configured to:
determine that the sensed hole conduction current is above a reference amount (para. 243; " the read operation using hole conduction is referred to as “PMOS read”. See also Fig. 23(2) where it illustrates the P-Pass region which are the memory cells for which the hole conduction current is above a reference amount.).
and determine that the memory cell did not pass the first erase verify test (Fig. 28 where it illustrates steps S22 and S26 which determine if one (or the other) erase verify tests pass or fail).
Regarding claim 5, Lien Maeda and Wong combined disclose the limitations of claim 1.
As applied, Song further discloses wherein the control circuit is further configured to:
determine that the sensed hole conduction current is not above a reference amount (para. 243; " the read operation using hole conduction is referred to as “PMOS read”. See also Fig. 23(2) where it illustrates the region below (to the left) of the P-PASS region which are the memory cells for which the hole conduction current is not above a reference amount.)
and determine that the memory cell passed the first erase verify test (Fig. 28 where it illustrates steps S22 and S26 which determine if one (or the other) erase verify tests pass or fail).
Regarding claim 6, Lien Maeda and Wong combined disclose the limitations of claim 1.
As applied, Song further discloses wherein the control circuit is further configured to:
determine that the sensed electron conduction current is above a reference amount (para. 243; "the read operation using electron conduction is referred to as “NMOS read”. See also Fig. 23(1) where it illustrates the N-PASS region which are the memory cells for which the electron conduction current is above a reference amount.
and determine that the memory cell passed the second erase verify test (Fig. 28 where it illustrates steps S22 and S26 which determine if one (or the other) erase verify tests pass or fail).
Regarding claim 7, Lien Maeda and Wong combined disclose the limitations of claim 1.
As applied, Song further discloses wherein the control circuit is further configured to:
determine that the sensed electron conduction current is not above a reference amount (para. 243; "the read operation using electron conduction is referred to as “NMOS read”. See also Fig. 23(1) where it illustrates the region above (to the right) of the N-PASS region which are the memory cells for which the electron conduction current is not above a reference amount.).
and determine that the memory cell did not pass the second erase verify test (Fig. 28 where it illustrates steps S22 and S26 which determine if one (or the other) erase verify tests pass or fail).
Regarding claim 8, Lien, Maeda and Wong combined disclose the limitations of claim 1.
As applied, Maeda further discloses wherein the control circuit is further configured to:
determine that the memory cell passed the first erase verify test (Fig. 28 where it illustrates step S22 (YES) which determines the first erase verify passing condition.);
and set a flag associated with the word line to a first value to indicate that the word line is to be inhibited from receiving subsequent erase pulses (Fig. 28 where it illustrates step S22 (YES path) for memory cells that have passed the first erase verify and bypass the subsequent erase operation step S24 and go directly to the END of the process. It is noted that the term "flag" is not explicitly defined in the instant application but merely indicated as an exemplary Boolean condition variable analogous to Madea's S22 flow chart decision diamond and subsequent conditional process branch.)
Regarding claim 9, Lien, Maeda and Wong combined disclose the limitations of claim 1.
As applied, Maeda further discloses wherein the control circuit is further configured to:
determine that the memory cell did not pass the first erase verify test (Fig. 28 where it illustrates step S22 (NO) which determines the first erase verify non-passing condition.);
and maintain a flag associated with the word line to a second value to indicate that the word line is not to be inhibited from receiving subsequent erase pulses (Fig. 28 where it illustrates step S22 (NO path) for memory cells that have not passed the first erase verify and proceed to the subsequent erase operation step S24.)
Regarding claim 10, Lien, Maeda and Wong combined disclose the limitations of claim 1.
As applied, Lien further discloses wherein the control circuit is further configured to:
determine that the memory cell did not pass the second erase verify test (Fig. 12 where it illustrates the erase operation loop method and specifically step 1205 which is one of N erase-verify tests;
and apply an additional erase pulse to the word line (Fig. 12 where it illustrates the erase not being complete and looping back to step 1204 for an additional erase pulse).
Regarding independent claim 11, Lien discloses an apparatus comprising:
an erase block comprising a plurality of memory cells and a plurality of word lines coupled to the memory cells (col. 3, ln. 36-37; "the memory cells in a block are erased to an erase state." See also Fig. 7);
and a control circuit coupled to the erase block, the control circuit configured to:
applying an erase pulse to the plurality of word lines (Fig. 7:124 Row decoder);
performing a second erase verify test using a electron erase verify level on each of the selected word lines and a positive bias to unselected word lines to detect slow-to-erase word lines (col. 3, ln. 49-50; "the erase operation involves multiple erase-verify iterations". See also Fig. 9 which illustrates the application of positive erase verify voltage VvEr. See also col. 18, ln. 25-27 "The erase operation is completed when the Vth of all, or nearly all, of the memory cells is below a verify voltage of VvEr". It is well understood in the art that the standard erase verify operation (e.g., electron erase verify) necessarily sets any unselected memory cells in a given string to a positive voltage.);
determining that the second one of the word lines does not pass the second erase verify test (Fig. 12 where it illustrates step 1205 erase verify, and step 1206 (F path));
and applying an additional erase pulse to the plurality of word lines (Fig. 12 where it illustrates step 1204 which applies another erase pulse to the memory cells which failed the previous erase-verify test) while floating the first one of the word lines (col. 19, ln. 27-30 "one or more blocks are erased in a plane while one or more other blocks are inhibited from being erased, where all of the blocks are on a common p-well. The word line voltages can be floated").
Lien discloses a first and second erase verify test but is silent about the specific type of current-mode sensing used in the erase-verify operation.
However, Maeda teaches performing a first erase verify test using a hole erase verify level on each of the selected word lines (para. 174; "the semiconductor memory device 1 according to the first embodiment can execute an erase verify operation in units of the block BLK and an erase verify operation in units of the string unit SU by a read operation using hole conduction.);
determining that a first one of the word lines passes the first erase verify test (Fig. 28 where it illustrates steps S22 and S26 which determine passing/failing of one (or the other) erase verify operations);
determining that a second one of the word lines does not pass the first erase verify test (Fig. 28 where it illustrates steps S22 and S26 which determine passing/failing of one (or the other) erase verify operations);
Lien and Maeda are silent with respect to applying a negative voltage to the unselected word lines during the first erase verify test.
However, Wong teaches and a negative bias to unselected word lines to detect fast-to-erase word lines (col. 6, ln. 45-49; "During a read or verify operation, word-line decoder 120 applies a negative voltage (e.g., approximately -3 volts) to the unselected ones of word lines WL1 to WLM, where the unselected word-lines are the ones that do not contain the memory cell selected for the read or verify operation")
Lien, Maeda, and Wong are from the same field of endeavor as applicant’s invention directed to erase-verify operation in non-volatile memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the erase verify operations of Lien by incorporating the hole conduction erase verify taught by Maeda combined with the negative unselected word line bias taught by Wong. Doing so would improve the efficiency of the erase-verify operation and reliability of the memory device.
Regarding claim 15, Lien, Maeda and Wong combined disclose the limitations of claim 11.
As applied, Maeda further discloses wherein performing a first erase verify test comprises
sensing a hole conduction current in memory cells coupled to the word lines (para. 174; "the semiconductor memory device 1 according to the first embodiment can execute an erase verify operation in units of the block BLK and an erase verify operation in units of the string unit SU by a read operation using hole conduction.).
Regarding claim 16, Lien, Maeda and Wong combined disclose the limitations of claim 11.
As applied, Lien further discloses wherein performing a second erase verify test comprises sensing an electron conduction current in memory cells coupled to the word lines (col. 3, ln. 49-50; "the erase operation involves multiple erase-verify iterations". See also Fig. 9 which illustrates the application of positive erase verify voltage VvEr. Additionally, the specification of the instant application recites: [00227] "In an embodiment, electron erase verify level eEVFY is equal to the conventional erase verify level")
Regarding independent claim 19, Lien discloses a method comprising:
applying an erase pulse to a plurality of word lines of an erase block of non-volatile memory cells (col. 3, ln. 36-37; "the memory cells in a block are erased to an erase state." See also Fig. 7);
floating the first selected one of the word lines (col. 19, ln. 27-30; "In some cases, one or more blocks are erased in a plane while one or more other blocks are inhibited from being erased, where all of the blocks are on a common p-well. The word line voltages can be floated." Note also Fig. 12 where it illustrates another erase pulse if the erase-verify test is failed);
performing an electron erase verify test by applying an electron erase verify level to a second selected one of the word lines selected word lines applying a positive bias to unselectd word line to detect slow-to-erase word lines and sensing an electron conduction current in memory cells coupled to the second selected one of the word lines (col. 3, ln. 49-50; "the erase operation involves multiple erase-verify iterations". See also Fig. 9 which illustrates the application of positive erase verify voltage VvEr. See also col. 18, ln. 25-27 "The erase operation is completed when the Vth of all, or nearly all, of the memory cells is below a verify voltage of VvEr". It is well understood in the art that the standard erase verify operation (e.g., electron erase verify) necessarily sets any unselected memory cells in a given string to a positive voltage.);
determining that the second selected one of the word lines does not pass the electron erase verify test; and applying an additional erase pulse to the second selected one of the word lines (Fig. 12 where it illustrates the erase verify test step 1205 and the subsequent loop back to step 1205 for another erase pulse if the test failed).
Lien discloses a first and second erase verify test but is silent about the specific type of current-mode sensing used in the erase-verify operation.
However, Maeda teaches performing a hole erase verify test by applying a hole erase verify level to a first selected one of the word lines (para. 174; "the semiconductor memory device 1 according to the first embodiment can execute an erase verify operation in units of the block BLK and an erase verify operation in units of the string unit SU by a read operation using hole conduction.),
determining that the first selected one of the word lines passes the hole erase verify test (Fig. 28 where it illustrates steps S22 and S26 which determine passing/failing of one (or the other) erase verify operations;
Lien and Maeda are silent with respect to applying a negative voltage to the unselected word lines during the first erase verify test.
However, Wong teaches applying a negative bias to unselected word lines to detect fast-to-erase word lines and sensing a hole conduction current in memory cells coupled to the first selected one of the word lines (col. 6, ln. 45-49; "During a read or verify operation, word-line decoder 120 applies a negative voltage (e.g., approximately -3 volts) to the unselected ones of word lines WL1 to WLM, where the unselected word-lines are the ones that do not contain the memory cell selected for the read or verify operation");
Lien, Maeda, and Wong are from the same field of endeavor as applicant’s invention directed to erase-verify operation in non-volatile memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the erase verify operations of Lien by incorporating the hole conduction erase verify taught by Maeda combined with the negative unselected word line bias taught by Wong. Doing so would improve the efficiency of the erase-verify operation and reliability of the memory device.
Claims 3, 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al. (US 11335411; “Lien” – of record) in view of Maeda (US 20200402597), and further in view of Wong (US 62855593), and further in view of Pan et al. (US 20030147279; “Pan” – of record).
Regarding claim 3, Lien, Maeda and Wong combined disclose the limitations of claim 2.
Lien, Maeda and Wong combined are silent with respect to relative levels of the erase verify.
However, Pan teaches wherein performing the second erase verify test comprises
applying a second erase verify level to the word line, the second erase verify level greater than the first erase verify level (para. 22; "a second erase verify level which is greater than the first erase verify level")
Lien, Maeda and Wong combined along with Pan are from the same field of endeavor as applicant’s invention directed to erase operations in non-volatile memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lien's array and control circuit structure with the teachings of Maeda and Wong’s dual current-mode sensing and with Pan’s method to tighten the erase threshold voltage distribution. Doing so would result in less over erase conditions and therefore improve memory cell longevity.
Regarding claim 20, Lien, Maeda and Wong combined disclose the limitations of claim 19.
Lien, Maeda and Wong are silent with respect to relative levels of the erase verify.
However, Pan teaches wherein the electron erase verify level is greater than the hole erase verify level (para. 22; "a second erase verify level which is greater than the first erase verify level". It is noted that in the instant application, the electron erase verify level is the second level and the hole erase verify level is the first level).
Lien, Maeda and Wong combined along with Pan are from the same field of endeavor as applicant’s invention directed to erase operations in non-volatile memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lien’s array and control circuit structure with the teachings of Maeda and Wong’s dual current-mode sensing and with Pan’s method to tighten the erase threshold voltage distribution. Doing so would result in less over erase conditions and therefore improve memory cell longevity.
Response to Arguments
Applicant's arguments filed March 13, 2026, have been fully considered but they are not persuasive. Although the amendments to independent claims 1, 11, and 19 narrow the claim scope and are not disclosed by the previously applied references, the newly added features required further consideration and search. This search resulted in the application of new references. The claimed subject matter remains unpatentable under 35 U.S.C. § 103 over the combination of the previously applied references and the newly cited references. This constitutes a new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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