DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 06/05/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 05/08/2024.
Oath/Declaration
The oath or declaration filed on 03/22/2024 is acceptable.
Election/Restrictions
Applicant’s election, without traverse, species I, as directed to embodiments of Figure 2A (claims 1-7, 9-10 and 18-19), in the “Response to Election / Restriction Filed” filed on 06/05/2026 is acknowledged.
However, the features of claim 2 such as “wherein each of the first gate lines comprises a first sub-gate and a first main gate, a first sub-gate insulating layer is on an upper surface of the first sub-gate and a first main gate insulating layer is on an upper surface of the first main gate, and the second gate line comprises a second sub-gate and a second main gate, a second sub-gate insulating layer is on an upper surface of the second sub-gate, and a second main gate insulating layer is on an upper surface of the second main gate” does not support elected species I, (Figure.[2A]). It appears feature of claim 2 read on non-elected species, as discloses in (Fig 2B, Para [ 0015-0016], [0102-0109]).
Therefore, claim 2 is withdrawn. Claims 3-7 are withdrawn based on the dependency of claim 2.
The features of claim 10 such as “wherein one of the first channels that does not overlap the second gate line in the vertical direction is free of another channel thereon.” does not support elected species I, (Figure. [2A]). It appears feature of claim 2 read on non-elected species, as discloses in (Fig 2B, Para [ 0015-0016], [0102-0109]). Therefore, claim 10 is withdrawn.
The features of claim 18 such as “ a first lower signal line electrically connected to the first lower source/drain contact; a second lower signal line electrically connected to the second lower source/drain contact; and a third lower signal line electrically connected to the first lower gate contact, wherein each of the first gate lines comprises a first sub-gate and a first main gate, a first sub-gate insulating layer is on an upper surface of the first sub-gate, and a first main gate insulating layer is on an upper surface of the first main gate, the second gate line comprises a second sub-gate and a second main gate, a second sub-gate insulating layer is on an upper surface of the second sub-gate, and a second main gate insulating layer is on an upper surface of the second main gate, and the fifth insulating layer overlaps each of the second gate line and the third gate line in the first horizontal direction” does not support elected species I, (Figure. [2A]). It appears feature of claim 18 read on non-elected species, as discloses in (Fig 2B, Para [ 0015-0016], [0102-0109]).
Therefore, claim 18 is withdrawn. Claim 19 is withdrawn based on the dependency of claim 18.
This office action considers claims 1-20 are thus pending for prosecution of which, claims 2-8 and 10-20 are withdrawn.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann et al (US 2020/0373203 A1; hereafter Liebmann) in view of Hwang et al (US 2008/0137389 A1; hereafter Hwang).
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Regarding claim 1. Liebmann discloses a multi-stack semiconductor device, comprising:
a substrate (Fig 1B, “The CFET transistor stack 200 can include four CFET devices 202-208 that are stacked over a substrate (not shown)” Para [ 0031]);
first channels (Fig 1, channels [ N1, P1], Para [ 0031-0032]) over the active area in a vertical direction perpendicular to an upper surface of the substrate (Fig 1B, “The CFET transistor stack 200 can include four CFET devices 202-208 that are stacked over a substrate (not shown)” Para [ 0029]) and spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate (Fig 1B, “The CFET transistor stack 200 can include four CFET devices 202-208 that are stacked over a substrate (not shown)” Para [ 0029]);
first gate lines (transistors [ N1, P1], gate structure 212 can have one or more gate electrodes 214, construed as first gate lines) on the respective first channels (channels [ N1, P1], Para [ 0031-0033]), each of the first gate lines extending in a second horizontal direction intersecting the first horizontal direction (transistors [ N1, P1], gate structure 212 can have one or more gate electrodes 214, construed as gate lines), and spaced apart from each other in the first horizontal direction (transistors [ N1, P1], gate structure 212 can have one or more gate electrodes 214, construed as gate lines);
first source/drain areas (transistors [ N1, P1], source region 218 and the drain region 216, Para [ 0031-0033]) on opposing sides of each of the first channels in the first horizontal direction (source region 218 and the drain region 216, Para [ 0031-0033]);
a second channel (Fig 1, channels [ N2, P2], Para [ 0031-0033]) over and spaced apart from any one of the first gate lines in the vertical direction (transistors [ N1, P1], gate structure 212 can have one or more gate electrodes 214, construed as gate lines);
a second gate line (transistors [ N2, P2], gate structure 212 can have one or more gate electrodes 214, construed as second gate lines) on the second channel (Fig 1B, channels [ N2, P2], Para [ 0031-0033]) and extending in the second horizontal direction (transistors [ N2, P2], gate structure 212 can have one or more gate electrodes 214, construed as second gate lines);
second source/drain areas ([ N2, P2], source region 218 and the drain region 216, Para [ 0031-0033]) on opposing sides of the second channel in the first horizontal direction (source region 218 and the drain region 216, Para [ 0031-0033]);
a third channel over (Fig 1B, channels [ N3, P3], Para [ 0031-0033]) and spaced apart from the second gate line in the vertical direction;
a third gate line (transistors [ N4, P4], gate structure 212 can have one or more gate electrodes 214, construed as third gate lines) on the third channel (Fig 1B, channels [ N4, P4], Para [ 0031-0033]) and extending in the second horizontal direction (transistors [ N4, P4], gate structure 212 can have one or more gate electrodes 214, construed as third gate lines);
third source/drain areas ([ N4, P4], source region 218 and the drain region 216, Para [ 0031-0033]) on opposing sides of the third channel in the first horizontal direction (Fig 1B, channels [ N4, P4], Para [ 0031-0033]); and
Liebmann further discloses contact array (e.g., 210 in FIG. 1B, Para [ 0036]).
But Liebmann does not disclose explicitly a device isolation layer defining an active area of the substrate; first channels over the active area in a vertical direction perpendicular to an upper surface of the substrate and a first lower source/drain contact extending in the vertical direction and electrically connected to a given one of the first source/drain areas, a given one of the second source/drain areas, and a given one of the third source/drain areas.
In a similar field of endeavor, Hwang discloses a device isolation layer defining an active area of the substrate ( Fig [2,6A], Para [ 0057] discloses “first stack structure A1 may include a substrate 1 in which a trench type device isolation film 2 that defines an active area is formed”); first channels over the active area in a vertical direction perpendicular to an upper surface of the substrate ( Fig [2,6A], Para [ 0057-0060]) and a first lower source/drain contact extending in the vertical direction and electrically connected to a given one of the first source/drain areas ( Fig [2,6A], Para [0043-0048, 0057-0060]), a given one of the second source/drain areas ( Fig [2,6A], Para [0043-0048, 0057-0060]), and a given one of the third source/drain areas ( Fig [2,6A], Para [0043-0048, 0057-0060]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Liebmann in light of Hwang teaching “a device isolation layer defining an active area of the substrate ( Fig [2,6A], Para [ 0057] discloses “first stack structure A1 may include a substrate 1 in which a trench type device isolation film 2 that defines an active area is formed”); first channels over the active area in a vertical direction perpendicular to an upper surface of the substrate ( Fig [2,6A], Para [ 0057-0060]) and a first lower source/drain contact extending in the vertical direction and electrically connected to a given one of the first source/drain areas ( Fig [2,6A], Para [0043-0048, 0057-0060]), a given one of the second source/drain areas ( Fig [2,6A], Para [0043-0048, 0057-0060]), and a given one of the third source/drain areas ( Fig [2,6A], Para [0043-0048, 0057-0060])” for further advantage such as to provide multi-stack memory device having a predetermined or given bit size by maintaining gap between the storage nodes arranged in different rows through connection with transistors.
Regarding claim 9. Liebmann in light of Hwang discloses the multi-stack semiconductor device of claim 1, Liebmann further discloses wherein a subset of the first gate lines (transistors [ N1, P1], gate structure 212 can have one or more gate electrodes 214, construed as first gate lines) spaced apart from each other in the first horizontal direction share a corresponding (transistors [ N1, P1], gate structure 212 can have one or more gate electrodes 214, construed as first gate lines) one of the first source/drain areas (transistors [ N1, P1], source region 218 and the drain region 216, Para [ 0031-0033]) between the subset of the first gate lines (transistors [ N1, P1], gate structure 212 can have one or more gate electrodes 214, construed as first gate lines).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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