CTNF 18/613,338 CTNF 84148 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim 15 objected to because of the following informalities: Claim 15 “the second portion of the first gate line” should be “[[the]] a second portion of the first gate line” as claim 15 introduces a second portion of the first gate line for the first time . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim 1 is rejected under 35 U.S.C. § 102( a)(1 ) as being anticipated by US 9,929,160 B1 to Lee et al., “Lee” . Regarding claim 1, Lee discloses an integrated circuit device (e.g. FIG. 2A) comprising: a first fin-type active region (UP1 on right side of isolation region IR, column 4 lines 28-30) extending in a first horizontal direction (D1) on a substrate (100); a first nano-sheet stack (stack of NS1 on left side of SD1 adjacent to isolation region IR) comprising a first plurality of nano-sheets (NS1) arranged on the first fin-type active region; a first gate line (dummy gate DE, column 5 lines 18-20) extending in a second horizontal direction (D2) intersecting the first horizontal direction, on the first fin-type active region; a vertical structure (SD1, column 5 lines 38-43) contacting each of the first plurality of nano-sheets (NS1) included in the first nano-sheet stack; and a first gate dielectric layer (GI and GP together , column 4 line 66 to column 5 line 2) disposed between the first gate line (DE) and the first plurality of nano-sheets (NS1) and between the first gate line (DE) and the vertical structure (SD1), wherein the first gate line (DE) comprises a first sub-gate portion disposed under each of the first plurality of nano-sheets (DE extends to between nanosheets NS1), the first gate dielectric layer (GI) comprises: a first portion (GI) disposed between the first gate line (DE) and the first plurality of nano-sheets (NS1); and a second portion (BP, column 11 lines 18-27) disposed between the first sub-gate portion (DE) and the vertical structure (SD1), and a thickness of the second portion (BP) in the second horizontal direction is greater than a thickness of the first portion in a vertical direction (as pictured) . 07-15-03-aia AIA Claim s 1,3,6-7,9,11,14-15 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by US 2023/0223442 A1 to CHIANG et al., “Chiang” . Regarding claim 1, Chiang discloses an integrated circuit device (FIG. 1C, FIG. 1E or 1F) comprising: a first fin-type active region (322 in region 20B, ¶ [0019],[0020]) extending in a first horizontal direction on a substrate; a first nano-sheet stack comprising a first plurality of nano-sheets (22C2, 22B2, 22A2, ¶ [0021]) arranged on the first fin-type active region (322); a first gate line (200B, ¶ [0017],[0018]) extending in a second horizontal direction intersecting the first horizontal direction, on the first fin-type active region (322); a vertical structure (306, ¶ [0035]) contacting each of the first plurality of nano-sheets (22C2, 22B2, 22A2) included in the first nano-sheet stack; and a first gate dielectric layer (FIG. 1E is zoomed in one of nanosheets in FIG. 1C, dielectric 600, ¶ [0026]) disposed between the first gate line (200B) and the first plurality of nano-sheets (22C2, 22B2, 22A2) and between the first gate line (200B) and the vertical structure (306), wherein the first gate line comprises a first sub-gate portion disposed under each of the first plurality of nano-sheets, the first gate dielectric layer (600) comprises: a first portion (portion surrounding the nanosheet, see Examiner-annotate figure below) disposed between the first gate line (290) and the first plurality of nano-sheets; and a second portion (portion adjacent 306, see Examiner-annotated figure below) disposed between the first sub-gate portion and the vertical structure, and a thickness (e.g. distance D1) of the second portion in the second horizontal direction is greater than a thickness of the first portion in a vertical direction (as pictured). PNG media_image1.png 675 921 media_image1.png Greyscale Regarding claim 3, Chiang discloses the integrated circuit device of claim 1, and Chiang further teaches wherein the first gate dielectric layer comprises a stacked structure comprising an interfacial dielectric layer (210, ¶ [0025]) and a high-k layer (600, ¶ [0026]). Regarding claim 6, Chiang discloses the integrated circuit device of claim 1, and Chiang further discloses a second fin-type active region (321 in region 20A) spaced apart from the first fin-type active region (322 in region 20B) in the second horizontal direction and extending in the first horizontal direction; a second nano-sheet stack (22C1, 22B1, 22A1, ¶ [0038]) disposed on the second fin-type active region (321 in region 20A), spaced apart from the first nano-sheet stack with the vertical structure (306) disposed therebetween, and comprising a second plurality of nano-sheets (22C1, 22B1, 22A1) in contact with the vertical structure (306); a second gate line (200A, ¶ [0017]) extending in the second horizontal direction, on the second fin-type active region (321 in region 20A), and spaced apart from the first gate line (200B) with the vertical structure (206) disposed therebetween; and a second gate dielectric layer (also 600) disposed between the second gate line (200A) and the second plurality of nano-sheets (22C1, 22B1, 22A1) and between the second gate line (200A) and the vertical structure (306), wherein the second gate line (200A) comprises: a second main gate portion disposed on the second nano-sheet stack (200A extends beyond and above nanosheets 22C1, 22B1, 22A1); and a second sub-gate portion disposed under each of the second plurality of nano- sheets (200A extends between nanosheets 22C1, 22B1, 22A1), the second gate dielectric layer (600) comprises (FIG. 1E): a first portion (all nanosheets are identical or mirrored, see Examiner-annotated figure above) disposed between the second gate line (200A) and the second plurality of nano-sheets (22C1, 22B1, 22A1); and a second portion (see Examiner-annotated figure above) disposed between the second sub-gate portion and the vertical structure, and a thickness (D1) of the second portion in the second horizontal direction is greater than the thickness of the first portion in the vertical direction (as pictured). Regarding claim 7, Chiang discloses an integrated circuit device (FIG. 1C, FIG. 1E or 1F) comprising: a substrate (110) comprising a first region (20B) and a second region (20A); a first fin-type active region (322 in 20B) extending in a first horizontal direction on the first region; a second fin-type active region (321 in 20A) extending in the first horizontal direction on the second region and spaced apart (by 306) from the first fin-type active region in a second horizontal direction intersecting the first horizontal direction; a plurality of nano-sheets (22C2, 22B2, 22A2, and 22C1, 22B1, 22A1, ¶ [0016],[0021]) on the first fin-type active region (322) and the second fin-type active region (321) and spaced apart from the first fin-type active region and the second fin-type active region in a vertical direction; a first gate line (200B, ¶ [0017],[0018]) on the first fin-type active region (322) and extending in the second horizontal direction; a second gate line (200A, ¶ [0016],[0017]) on the second fin-type active region (321) and extending in the second horizontal direction; a vertical structure (306, ¶ [0035]) disposed between the first gate line (200B) and the second gate line (200A) and contacting each of the plurality of nano-sheets; and a first gate dielectric layer (FIG. 1E is zoomed in one of nanosheets in FIG. 1C, dielectric 600, ¶ [0026]) disposed between the first gate line (200B) and the plurality of nano-sheets and between the first gate line and the vertical structure (306), wherein the first gate line (200B) comprises: a first main gate portion (upper portion of 200B near 297) disposed at a higher vertical level than the plurality of nano-sheets (22C2, 22B2, 22A2) on the first fin-type active region (322); and a first sub-gate portion (portions of 200B between nanosheets) disposed under each of the plurality of nano-sheets on the first fin-type active region (322), the first gate dielectric layer (600) comprises: a first portion (portion surrounding the nanosheet, see Examiner-annotate figure above) disposed between the first gate line (200B) and the plurality of nano-sheets (22C2, 22B2, 22A2) on the first fin-type active region (322); and a second portion (portion adjacent 306, see Examiner-annotated figure above) disposed between the first sub-gate portion and the vertical structure (306), and a thickness (e.g. distance D1) of the second portion in the second horizontal direction is greater than the thickness of the first portion in the second horizontal direction (as pictured). Regarding claim 9, Chiang discloses the integrated circuit device of claim 7, and Chiang further discloses wherein the first fin-type active region (322) and the second fin-type active region (321) have different conductivity types (n-type and p-type for different gates 200B and 200A, ¶ [0073]), and the vertical structure (306) comprises a dielectric material (¶ [0035]). Regarding claim 11, Chiang discloses the integrated circuit device of claim 7, further comprising a second gate dielectric layer (also 600) disposed between the second gate line (200A) and the plurality of nano-sheets (22C1, 22B1, 22A1) on the second fin-type active region (321 in 20A) and between the second gate line (200A) and the vertical structure (306), wherein the second gate line comprises: a second main gate portion (200A near 99) disposed at a higher vertical level than the plurality of nano-sheets (22C1, 22B1, 22A1) on the second fin-type active region (321 in 20A); and a second sub-gate portion (portion of 200A between nanosheets) disposed under each of the plurality of nano-sheets on the second fin-type active region (321 in 20A), the second gate dielectric layer (600) comprises: a first portion (portion surrounding the nanosheet, see Examiner-annotate figure above) disposed between the second gate line (200A) and the plurality of nano-sheets (22C1, 22B1, 22A1) on the second fin-type active region; and a second portion (portion adjacent 306, see Examiner-annotated figure above) disposed between the second sub-gate portion (200A) and the vertical structure (306), and a thickness (e.g. distance D1) of the second portion of the second gate dielectric layer in the second horizontal direction is greater than a thickness of the first portion of the second gate dielectric layer in the second horizontal direction. Regarding claim 14, Chiang discloses the integrated circuit device of claim 7, and Chiang further discloses wherein the first gate dielectric layer comprises a stacked structure of an interfacial dielectric layer (210, ¶ [0025]) and a high-k layer (600, ¶ [0026]). Regarding claim 15, Chiang discloses the integrated circuit device of claim 7, and Chiang further discloses wherein a thickness of [[the]] a second portion of the first gate line (200B) in the second horizontal direction is greater than a thickness of the first portion of the first gate line (200B) in the vertical direction (see Examiner-annotated figure below): PNG media_image2.png 475 524 media_image2.png Greyscale Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. § 103 as being unpatentable over US 2023/0223442 A1 to CHIANG et al., “Chiang” . Regarding claim 8, Chiang discloses the integrated circuit device of claim 7, and Chiang further teaches wherein the vertical structure (306) comprises an insulation material (¶ [0035]). Chiang fails to clearly anticipate wherein the first fin-type active region (322 in 20B) and the second fin-type active region (321 in 10A) have a same conductivity type. However, Chiang teaches selecting suitable semiconductor materials for n-type and p-type FETs (¶ [0015],[0024],[0028],[0054],[0055]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chiang with both the first and second fin-type active regions being of the same conductivity type in the process of selecting multiple regions as both either n-type or p-type in the process of building CMOS logic and since it has been held in KSR Int'l Co. v. Teleflex Inc ., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include: (A) Combining prior art elements according to known methods to yield predictable results; (B) Simple substitution of one known element for another to obtain predictable results; (C) Use of known technique to improve similar devices (methods, or products) in the same way; (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results; (E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success; (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art; (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention, wherein in the instant case one having ordinary skill in the art would have been capable of and found it obvious to (A) combining prior art elements (e.g. a plurality of n-type or p-type regions) using the known integrating method of Chiang with the predictable and desired result of building CMOS logic . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 17-20 allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 2,4-5,10,12-13,16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Although prior art e.g. Chiang teaches integrating nanosheet FETs as discussed above, prior art fails to reasonably teach or suggest a first source/drain region disposed adjacent to the first gate line and contacting each of the first plurality of nano-sheets; a second source/drain region disposed adjacent to the second gate line and contacting each of the second plurality of nano-sheets; a third portion disposed between the first sub-gate portion and the first source/drain region, each of a thickness of the second portion of the first gate dielectric layer in the second horizontal direction and a thickness of the third portion of the first gate dielectric layer in the first horizontal direction is greater than the thickness of the first portion of the first gate dielectric layer in a vertical direction, the second gate dielectric layer comprises: a first portion disposed between the second gate line and the second plurality of nano-sheets; and a second portion disposed between the second sub-gate portion and the vertical structure, and a thickness of the second portion of the second gate dielectric layer in the second horizontal direction is greater than a thickness of the first portion of the second gate dielectric layer in the vertical direction, together with all of the other limitations of claim 17 as claimed . Claims 18-20 are allowable insofar as they depend upon and include all of the limitations of allowable claim 17 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Eric A. Ward/Primary Examiner, Art Unit 2891 Application/Control Number: 18/613,338 Page 2 Art Unit: 2891 Application/Control Number: 18/613,338 Page 3 Art Unit: 2891 Application/Control Number: 18/613,338 Page 4 Art Unit: 2891 Application/Control Number: 18/613,338 Page 5 Art Unit: 2891 Application/Control Number: 18/613,338 Page 6 Art Unit: 2891 Application/Control Number: 18/613,338 Page 7 Art Unit: 2891 Application/Control Number: 18/613,338 Page 8 Art Unit: 2891 Application/Control Number: 18/613,338 Page 9 Art Unit: 2891 Application/Control Number: 18/613,338 Page 10 Art Unit: 2891 Application/Control Number: 18/613,338 Page 11 Art Unit: 2891 Application/Control Number: 18/613,338 Page 12 Art Unit: 2891
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