DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 3/22/2024 that has been entered, wherein claims 1-20 are pending, claims 21-25 are canceled.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-8, 11-12 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Phatak et al. (US 2016/0133691 A1).
Regarding claim 1, Phatak teaches a capacitor structure(please see examiner annotated Fig. 2, ID-7, ID-8) comprising:
an upper electrode(TEC conductor, Fig. 2);
a lower electrode(please see examiner annotated Fig. 2) including a lower electrode film(BEC conductor) and a lower interface electrode film(Bulk dielectric layer);
a capacitor dielectric film(upper High WF layer) between the lower electrode(please see examiner annotated Fig. 2) and the upper electrode(TEC conductor, Fig. 2); and
an interface blocking film(upper Interface layer, ¶0057-58) between the lower electrode(please see examiner annotated Fig. 2) and the capacitor dielectric film(upper High WF layer), the interface blocking film(upper Interface layer, ¶0057-58) being in contact with the capacitor dielectric film(upper High WF layer) and the lower interface electrode film(Bulk dielectric layer),
wherein the interface blocking film(upper Interface layer, ¶0057-58) includes a first metal oxide(AlOx ID-7, TiOx ID-8) containing a first metal element(Al ID-7, Ti ID-8),
the lower interface electrode film(Bulk dielectric layer) includes a second conductive metal oxide(ZrOx) containing a second metal element(Zr) different from the first metal element(Al ID-7, Ti ID-8),
the capacitor dielectric film(upper High WF layer) does not include the first metal oxide(AlOx ID-7, TiOx ID-8), and
a thickness(3-7nm) of the lower interface electrode film(Bulk dielectric layer) is greater than a thickness(0.1-2nm) of the interface blocking film(upper Interface layer, ¶0057-58).
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Regarding claim 2, Phatak teaches the capacitor structure of claim 1, wherein the lower electrode(please see examiner annotated Fig. 2) further includes a lower insertion electrode film(lower Interface layer) disposed between the lower electrode film(BEC conductor) and the lower interface electrode film(Bulk dielectric layer),
the lower electrode film(BEC conductor) includes a third metal element(Ti), and
the lower insertion electrode film(lower Interface layer) includes a third metal oxide(TiOx) containing the third metal element(Ti).
Regarding claim 3, Phatak teaches the capacitor structure of claim 2, wherein a thickness(0.1-2nm) of the lower insertion electrode film(lower Interface layer) is smaller than a thickness(3-7nm) of the lower interface electrode film(Bulk dielectric layer).
Regarding claim 4, Phatak teaches the capacitor structure of claim 2, wherein the third metal element(Ti) is different from the second metal element(Zr).
Regarding claim 7, Phatak teaches the capacitor structure of claim 1, wherein the first metal oxide(AlOx ID-7, TiOx ID-8) is a single metal oxide(AlOx ID-7, TiOx ID-8).
Regarding claim 8, Phatak teaches the capacitor structure of claim 1, wherein the first metal element(Al ID-7, Ti ID-8) includes at least one of tin (Sn), titanium (Ti) (Ti ID-8), nickel (Ni), cobalt (Co) and molybdenum (Mo).
Regarding claim 11, Phatak teaches a capacitor structure comprising:
an upper electrode(TEC conductor, Fig. 2);
a lower electrode(please see examiner annotated Fig. 2) including a lower electrode film(BEC conductor), a lower interface electrode film(Bulk dielectric layer), and a lower insertion electrode film(lower Interface layer) between the lower electrode film(BEC conductor) and the lower interface electrode film(Bulk dielectric layer);
a capacitor dielectric film(upper High WF layer) between the lower electrode(please see examiner annotated Fig. 2) and the upper electrode(TEC conductor, Fig. 2); and
an interface blocking film(upper Interface layer, ¶0057-58) between the lower electrode(please see examiner annotated Fig. 2) and the capacitor dielectric film(upper High WF layer), the interface blocking film(upper Interface layer, ¶0057-58) being in contact with the capacitor dielectric film(upper High WF layer) and the lower interface electrode film(Bulk dielectric layer),
wherein the interface blocking film(upper Interface layer, ¶0057-58) includes a first metal oxide(AlOx ID-7, TiOx ID-8) containing a first metal element(Al ID-7, Ti ID-8),
the lower interface electrode film(Bulk dielectric layer) includes a second conductive metal oxide(ZrOx) containing a second metal element(Zr) different from the first metal element(Al ID-7, Ti ID-8),
the lower electrode film(BEC conductor) includes a third metal element(Ti), and
the lower insertion electrode film(lower Interface layer) includes a third metal oxide(TiOx) containing the third metal element(Ti).
Regarding claim 12, Phatak teaches the capacitor structure of claim 11, wherein the second metal element(Zr) is different from the third metal element(Ti).
Regarding claim 15, Phatak teaches the capacitor structure of claim 11, wherein a thickness(3-7nm) of the lower interface electrode film(Bulk dielectric layer) is greater than a thickness(0.1-2nm) of the lower insertion electrode film(lower Interface layer) and a thickness(0.1-2nm) of the interface blocking film(upper Interface layer, ¶0057-58).
Regarding claim 16, Phatak teaches the capacitor structure of claim 11, wherein the first metal oxide(AlOx ID-7, TiOx ID-8) is a single metal oxide(AlOx ID-7, TiOx ID-8), and the capacitor dielectric film(upper High WF layer) does not include the first metal oxide(AlOx ID-7, TiOx ID-8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Phatak et al. (US 2016/0133691 A1).
Regarding claim 10, Phatak teaches the capacitor structure of claim 1, wherein the thickness(0.1-2nm) of the interface blocking film(upper Interface layer, ¶0057-58) is 10Å or less(0.1-2nm=1-20 Å).
Phatak does not explicitly state the thickness(3-7nm) of the lower interface electrode film(Bulk dielectric layer) is 5Å to 20Å. However Phatak does disclose a range (3-7nm=30-70 Å) close to the claimed 5Å to 20Å. Accordingly, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to make the thickness of the lower interface electrode film 5Å to 20Å since it has been held that when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art. Please see MPEP 2144.05.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2016/0079247 A1) in view of Phatak et al. (US 2016/0133691 A1).
Regarding claim 18, Lim teaches a semiconductor memory device(Fig. 9) comprising:
a substrate(100) including an active region(103, ¶0101) defined by an element isolation(105, ¶0101), the active region(103, ¶0101) extending in a first direction(DR1, Fig. 8, ¶0101) and including a first portion(107a, Fig. 8, ¶0108) and a second portion(107b, Fig. 8, ¶0108) defined on both sides of the first portion(107a, Fig. 8, ¶0108);
a word line(130, ¶0102) extended in a second direction(DR2, Fig. 8, ¶0102) different from the first direction(DR1, Fig. 8, ¶0101) in the substrate(100) and the element isolation(105, ¶0101) film, the word line(130, ¶0102) crossing between the first portion(107a, Fig. 8, ¶0108) of the active region(103, ¶0101) and the second portion(107b, Fig. 8, ¶0108) of the active region(103, ¶0101);
a bit line contact(160, ¶0104) connected to the first portion(107a, Fig. 8, ¶0108) of the active region(103, ¶0101);
a bit line(170, ¶0104) connected to the bit line contact(160, ¶0104) on the bit line contact(160, ¶0104) and extended in a third direction(DR3, Fig. 8, ¶0102) different from the first direction(DR1, Fig. 8, ¶0101) and the second direction(DR2, Fig. 8, ¶0102); and
a capacitor structure(C, ¶0117) including a lower electrode(200, ¶0117), a capacitor dielectric film(210, ¶0117) and an upper electrode(230, ¶0117), which are sequentially stacked on the lower electrode(200, ¶0117), the lower electrode(200, ¶0117) being connected to the second portion(107b, Fig. 8, ¶0108) of the active region(103, ¶0101),
wherein the lower electrode(200, ¶0117) includes:
a lower electrode film(200, ¶0117) connected to the second portion(107b, Fig. 8, ¶0108) of the active region(103, ¶0101).
Lim is not relied on to teach a capacitor structure(C, ¶0117) including a lower electrode(200, ¶0117) and an interface blocking film, a capacitor dielectric film(210, ¶0117) and an upper electrode(230, ¶0117), which are sequentially stacked on the lower electrode(200, ¶0117),
wherein the lower electrode(200, ¶0117) includes:
a lower electrode film(200, ¶0117) including a first metal element;
a lower insertion electrode film including a first metal oxide containing the first metal element; and
a lower interface electrode film including a second conductive metal oxide containing a second metal element,
the interface blocking film is in contact with the lower interface electrode film and the capacitor dielectric film(210, ¶0117), and includes a third metal oxide containing a third metal element different from the second metal element, and
a thickness of the lower interface electrode film is greater than a thickness of the lower insertion electrode film and a thickness of the interface blocking film.
Phatak teaches a semiconductor memory device(please see examiner annotated Fig. 2, ID-7, ID-8) comprising:
a capacitor structure including a lower electrode(please see examiner annotated Fig. 2) and an interface blocking film(upper Interface layer), a capacitor dielectric film(upper High WF layer) and an upper electrode(TEC conductor, Fig. 2), which are sequentially stacked on the lower electrode(please see examiner annotated Fig. 2),
wherein the lower electrode(please see examiner annotated Fig. 2) includes:
a lower electrode film(BEC conductor) including a first metal element(Al ID-7, Ti ID-8);
a lower insertion electrode film(lower Interface layer) including a first metal oxide(AlOx ID-7, TiOx ID-8) containing the first metal element(Al ID-7, Ti ID-8); and
a lower interface electrode film(Bulk dielectric layer) including a second conductive metal oxide(ZrOx) containing a second metal element(Zr),
the interface blocking film(upper Interface layer) is in contact with the lower interface electrode film(Bulk dielectric layer) and the capacitor dielectric film(upper High WF layer), and includes a third metal oxide(TiOx) containing a third metal element(Ti) different from the second metal element(Zr), and
a thickness(3-7nm) of the lower interface electrode film(Bulk dielectric layer) is greater than a thickness(0.1-2nm) of the lower insertion electrode film(lower Interface layer) and a thickness(0.1-2nm) of the interface blocking film(upper Interface layer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lim, to include a capacitor structure including a lower electrode and an interface blocking film, a capacitor dielectric film and an upper electrode, which are sequentially stacked on the lower electrode,
wherein the lower electrode includes: a lower electrode film including a first metal element; a lower insertion electrode film including a first metal oxide containing the first metal element; and a lower interface electrode film including a second conductive metal oxide containing a second metal element, the interface blocking film is in contact with the lower interface electrode film and the capacitor dielectric film, and includes a third metal oxide containing a third metal element different from the second metal element, and a thickness of the lower interface electrode film is greater than a thickness of the lower insertion electrode film and a thickness of the interface blocking film, as taught by Phatak, so that the interface layers may act as an oxygen sink, facilitate the crystallization of the electrode layer at lower temperature during a subsequent anneal treatment and provide barriers to leakage current through the film stack(¶0011).
Regarding claim 19, Lim teaches the semiconductor memory device of claim 18, but is not relied on to teach the second metal element is different from the first metal element.
Phatak teaches a semiconductor memory device(please see examiner annotated Fig. 2, ID-7, ID-8) wherein the second metal element(Zr) is different from the first metal element(Al ID-7, Ti ID-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lim so that the second metal element is different from the first metal element, as taught by Phatak, so that the interface layers may act as an oxygen sink, facilitate the crystallization of the electrode layer at lower temperature during a subsequent anneal treatment and provide barriers to leakage current through the film stack(¶0011).
Allowable Subject Matter
Claims 5-6, 9, 13-14, 17 and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 5, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the third metal element is the same as the second metal element,
the lower interface electrode film includes a first impurity element, and
the first impurity element includes at least one element from among groups 5 to 11 and 15 metal elements”.
Claim 6 depends on claim 5 and inherits it’s allowable subject matter.
Regarding dependent claim 9, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the second metal element includes at least one of indium (In), ruthenium (Ru), iridium (Ir), vanadium (V), tin (Sn), zinc (Zn), nickel (Ni), tungsten (W) and molybdenum (Mo)”
Regarding dependent claim 13, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the third metal element is the same as the second metal element,
the lower interface electrode film includes a first impurity element, and
the first impurity element includes at least one element from among groups 5 to 11 and 15 metal elements”.
Claim 14 depends on claim 13 and inherits it’s allowable subject matter.
Regarding dependent claim 17, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the second metal element includes at least one of indium (In), ruthenium (Ru), iridium (Ir), vanadium (V), tin (Sn), zinc (Zn), nickel (Ni), tungsten (W) and molybdenum (Mo)”
Regarding dependent claim 20, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the third metal element is the same as the second metal element,
the lower interface electrode film includes a first impurity element, and
the first impurity element includes at least one element from among groups 5 to 11 and 15 metal elements”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Krishnan et al. (US 2010/0315760 A1) Discloses a capacitor structure.
Mun et al. (US 2020/0058731 A1) Discloses a capacitor structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M DYKES/Examiner, Art Unit 2892
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