Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B in the reply filed on 8/4/26 is acknowledged.
No claims are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/4/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, 13, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung (US PGPub 2023/0028252).
Claim 11: Jung teaches (Fig. 1) a semiconductor package, comprising: a package substrate (100); a first chip stack 200-1, 200-2, 200-3) on the package substrate and comprising a plurality of first semiconductor chips that have an offset stack structure; a second semiconductor chip (200b) between the package substrate and the first chip stack; a plurality of bonding wires (215) that electrically connect the first semiconductor chips to the package substrate; a molding layer (600) that is on the package substrate, the second semiconductor chip, and the first chip stack; and a plurality of external terminals (105) on a bottom surface of the package substrate, wherein the first semiconductor chips and the second semiconductor chip are a same type [0020], wherein the second semiconductor chip is vertically aligned with a lowermost one of the first semiconductor chips, and wherein each thickness of the first semiconductor chips is the same as a thickness of the second semiconductor chip. The claim does not specify how the chips are vertically aligned. Their stacked natures reads on the claim as presented.
Claim 13: Jung teaches (Fig. 1) [0020] each of the first semiconductor chips and the second semiconductor chip comprises: a semiconductor substrate; a plurality of integrated elements on a top surface of the semiconductor substrate; and a wiring layer on the top surface of the semiconductor substrate, wherein the bonding wires electrically connect the wiring layers of neighboring first semiconductor chips from among the first semiconductor chips to each other or electrically connect the package substrate to the wiring layer of one of the first semiconductor chips. The chips taught by Jung are the same type as those in the instant application.
Claim 14: Jung teaches (Fig. 1,5) The semiconductor package of claim 11, wherein the second semiconductor chip has a width that is the same as a width of the lowermost one of the first semiconductor chips.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US PGPub 2023/0343746).
Claim 1: Park teaches (Fig. 2A) a semiconductor package, comprising: a package substrate (110); and a first chip stack (120A) on the package substrate, wherein the first chip stack comprises: a first semiconductor chip (DS) on the package substrate; a plurality of second semiconductor chips (a1-a4) that are on the first semiconductor chip and have an offset stack structure; and a plurality of first adhesive layers (125) that are respectively on a bottom surface of the first semiconductor chip and bottom surfaces of the second semiconductor chips, wherein the first semiconductor chip comprises: a first semiconductor substrate; a plurality of first integrated elements on a top surface of the first semiconductor substrate; and a first wiring layer on the top surface of the first semiconductor substrate [0035-0038], wherein a width of the first semiconductor chip and a width of a lowermost one of the second semiconductor chips are the same, and wherein the first semiconductor chip is electrically insulated from the package substrate and the second semiconductor chips. Park states the DS chip is a dummy chip that may be a silicon spacer. This implies that it could also be a semiconductor chip that could function but is just used as a placeholder.
Claim 2: Park teaches [0035-0038] the first semiconductor chip and the second semiconductor chips are a same type.
Claim 3: Park teaches (Fig. 2A) an entirety of the first semiconductor chip vertically overlaps the lowermost one of the second semiconductor chips.
Claim 4: Park teaches (Fig. 2A a first thickness of the first semiconductor chip is the same as a second thickness of each of the second semiconductor chips.
Claim 6: Park teaches [0035-0038] (Fig. 2A) a plurality of bonding wires that electrically connect the second semiconductor chips to the package substrate, wherein each of the second semiconductor chips comprises: a second semiconductor substrate; a plurality of second integrated elements on a top surface of the second semiconductor substrate; and a second wiring layer on the top surface of the second semiconductor substrate, wherein the bonding wires electrically connect one of the second semiconductor chips to the package substrate or electrically connect two of the second semiconductor chips to each other.
Claim 18: Park teaches (Fig. 2A) (see claim 1) semiconductor package, comprising: a package substrate; and a first chip stack on the package substrate, wherein the first chip stack comprises: a first semiconductor chip on the package substrate; a plurality of second semiconductor chips that are on the first semiconductor chip and have an offset stack structure; and a plurality of first adhesive layers that are respectively on a bottom surface of the first semiconductor chip and bottom surfaces of the second semiconductor chips, wherein the first semiconductor chip comprises: a first semiconductor substrate; a plurality of first integrated elements on a top surface of the first semiconductor substrate; and a first wiring layer on the top surface of the first semiconductor substrate, wherein a width of the first semiconductor chip and a width of a lowermost one of the second semiconductor chips are the same, wherein a planar area of the first semiconductor chip and a planar area of the lowermost one of the second semiconductor chips are the same, wherein a thickness of the first semiconductor chip and a thickness of the lowermost one of the second semiconductor chips are the same, wherein a thickness of each of the plurality of first adhesive layers is the same, and wherein the first semiconductor chip is electrically insulated from the package substrate and the second semiconductor chips.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US PGPub (2023/0343746), as applied to claim 1 above, and further in view of Taniguchi et al. (US PGPub (2023/0253366)
Regarding claim 5, as described above, Park substantially read on the invention as claimed, except Park does not teach a first thickness of the first semiconductor chip and a second thickness of each of the second semiconductor chips are in a range of about 30 micrometers to about 100 micrometers. Taniguchi teaches [0042] a first thickness of the first semiconductor chip and a second thickness of each of the second semiconductor chips are in a range of about 30 micrometers to about 100 micrometers. The subject matter as a whole would have been obvious to one of ordinary skill in the art at the time the invention was made to have selected the overlapping portion of the range disclosed by the reference because overlapping ranges have been held to be a prima facie case of obviousness, see In re Malagari, 182 U.S.P.Q. 549. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the thickness of the chips taught by Park to have the claimed range as they are known in the art.
Claim 7: Taniguchi teaches [0042] a thickness of each of the first adhesive layers is in a range of about 5 micrometers to about 20 micrometers. . The subject matter as a whole would have been obvious to one of ordinary skill in the art at the time the invention was made to have selected the overlapping portion of the range disclosed by the reference because overlapping ranges have been held to be a prima facie case of obviousness, see In re Malagari, 182 U.S.P.Q. 549. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the thickness of the chips taught by Park to have the claimed range as they are known in the art.
Claim(s) 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US PGPub 2023/0028252), as applied to claim 11 above, and further in view of Taniguchi et al. (US PGPub (2023/0253366)
Regarding claim 15, as described above, Jung substantially read on the invention as claimed, except Jung does not teach each thickness of the first semiconductor chips and the thickness of the second semiconductor chip are in a range of about 30 micrometers to about 100 micrometers. Taniguchi teaches [0042] a first thickness of the first semiconductor chip and a second thickness of each of the second semiconductor chips are in a range of about 30 micrometers to about 100 micrometers. The subject matter as a whole would have been obvious to one of ordinary skill in the art at the time the invention was made to have selected the overlapping portion of the range disclosed by the reference because overlapping ranges have been held to be a prima facie case of obviousness, see In re Malagari, 182 U.S.P.Q. 549. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the thickness of the chips taught by Jung to have the claimed range as they are known in the art.
Claim 16: Taniguchi teaches [0042] a plurality of adhesive layers that are respectively on a bottom surface of the second semiconductor chip and bottom surfaces of the first semiconductor chips, wherein a thickness of each of the adhesive layers is in a range of about 5 micrometers to about 20 micrometers.
Allowable Subject Matter
Claims 8-10, 12, 17 and 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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