DETAILED ACTION
This action is responsive to the application No. 18/613,754 filed on March 22, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species IV, directed to DEV4 shown in Fig. 23, corresponding to claims 1-10 and 12-16, in the reply filed on June 8, 2026, is acknowledged. Claim 11 is withdrawn from consideration.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Objections
Claims 15 and 16 are objected to because of the following informalities:
Claims 15 and 16 recite “FRD” and “IGBT”, respectively. When using abbreviations, acronyms, etc., the first time one is used, the full term should be spelled out. For example, claim 15 should recite “…a fast recovery diode (FRD)…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites a mixed crystal of silicon nitride and amorphous silicon, rendering the claim indefinite. A mixed crystal is understood to be a mix of various crystalline materials, while an amorphous material is understood to not be crystalline. However, it is further recognized that even “amorphous” materials may still contain small crystalline regions on the order of nanometers since semiconductor materials such as silicon when grown, while the bulk of the material has no long range order. It is unclear what Applicant regards as a mixed crystal that apparently comprises amorphous material.
Claim 14 recites “…second recesses recessed toward the first surface…”, rendering the claim indefinite. In view of the figures, and as best understood, it appears the recesses are recessed toward the second surface, however it is not particularly clear how directions are ascribed to recesses. It is unclear how to interpret second recesses recessed toward the first surface in view of Fig. 23.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 7-10, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2021/0125889).
(Re Claim 1) Chen teaches a semiconductor device comprising (see Figs. 1, 3, 4, and 8, ¶¶42-47 and 66-69):
a semiconductor substrate (3);
an insulating film (5, 51);
a first electrode (15) and a second electrode (8); and
a semi-insulating film (7), wherein the semiconductor substrate includes a first surface (top);
wherein the semiconductor substrate includes, in plan view, an element region (CR) and a termination region (TR) surrounding the element region (Fig. 1);
wherein the semiconductor substrate includes a first impurity region (17 and/or 18) formed on the first surface in the termination region;
wherein the insulating film covers the first surface in the termination region (Fig. 3);
wherein the first electrode is electrically connected to the first impurity region (15 connected to 17 at 14 and 17 is electrically connected to 18), and faces the first impurity region with the insulating film interposed therebetween (Fig. 3);
wherein the second electrode is disposed on the insulating film so as to surround the first electrode while being spaced apart from the first electrode in a plan view (Figs. 1 and 3);
wherein the semi-insulating film is disposed so as to extend across the insulating film between the first electrode and the second electrode in a plan view (Fig. 3);
wherein the semi-insulating film includes silicon and nitrogen (¶¶67-69);
wherein the ratio of the number of atoms of silicon to the sum of the number of atoms of silicon and the number of atoms of nitrogen in the semi-insulating film is 0.64 or more (Fig. 8 and ¶69, 2 Si : 1 N corresponds to a ratio of ~0.66).
(Re Claim 2) wherein the ratio of the number of atoms of silicon to the sum of the number of atoms of silicon and the number of atoms of nitrogen in the semi-insulating film is 0.74 or less (~0.66).
(Re Claim 5) wherein a thickness of the semi-insulating film is not less than 50 nm and not more than 1000 nm (Fig. 8: ~500 nm).
(Re Claim 7) wherein the first electrode and the second electrode are electrically connected by the semi-insulating film (Fig. 3, noting 6 is also semi-insulating).
(Re Claim 8) wherein the semiconductor substrate includes a second impurity region (from claim 1, first impurity region being 18, second region 17) formed on the first surface of the element region;
wherein the first electrode is connected to the second impurity region (15 connected to 17 at 14);
wherein an impurity concentration in the second impurity region (17 is p+) is higher than an impurity concentration in the first impurity region (18 is p-).
(Re Claim 9) further comprising a passivation film formed to cover the semi-insulating film (¶78).
(Re Claim 10) wherein the first electrode has an outer peripheral edge portion (edge of 15 near gate);
wherein the semi-insulating film has an inner peripheral edge portion (edge of 7 between gate and emitter);
wherein the semi-insulating film covers the second electrode (Fig. 3); and
wherein the inner peripheral edge portion covers the outer peripheral edge portion (Fig. 3).
(Re Claim 16) wherein an IGBT is formed in the element region (¶¶45-47)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied above, and further in view of Kahn et al. (US 2020/0083133) and Taylor et al. (US 2008/0286984).
(Re Claim 3) wherein some of the silicon is bonded to hydrogen in the semi-insulating film.
Chen is silent regarding wherein some of the silicon is bonded to hydrogen in the semi-insulating film. Chen teaches forming a silicon-rich silicon nitride semi-insulating film, however does not provide details of how the film is formed which would provide information as to the possible bonds and composition. A PHOSITA would be motivated to look to related art to teach methods for forming a silicon-rich silicon nitride film for Chen’s device. Related art from Kahn teaches forming the silicon-rich silicon nitride films by using silane and a nitrogen containing precursor (N2 or NH3) and achieving the silicon-rich film by controlling the gas flow ratio of the silicon precursor to the flow of the nitrogen precursor, and when forming the silicon-rich film, Si-H bonds are present in the film (¶¶39-42,60-66,87,91). Related art from Taylor similarly teaches forming silicon-rich silicon nitride using nitrogen and silane and also forms films comprising Si-H bonds (¶¶16-23,34-35,40-45). The Si-H bonds result from the residual H present from cracking the silane and, if ammonia is used, from the cracking the ammonia as well. Noting Taylor desires lower hydrogen content and uses a hydrogen-free nitrogen source (N2) and still incorporates hydrogen in the film from the silane. In view of the prior art teaching conventional methods for forming a silicon-rich silicon nitride film using silane and a nitrogen precursor, the films obviously will incorporate hydrogen from the precursor reactions and this will obviously result in some amount of hydrogen bonds present in the deposited film. A PHOSITA would find it obvious to select known, working, methods for forming the semi-insulating silicon-rich SiN film from the prior art, and when depositing the film using these processes, there will be Si-H bonds present.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied above, and further in view of Torchynska et al. (Thin Solid Films 581 (2015), pp. 65-69) and evidentiary reference Ho et al. (US 5,643,823).
(Re Claim 4, as best understood, see §112 rejection above) wherein the semi-insulating film is a mixed crystal of silicon nitride and amorphous silicon.
Chen is silent regarding the semi-insulating film is a mixed crystal of silicon nitride and amorphous silicon. Chen teaches forming a silicon-rich silicon nitride semi-insulating film, however does not provide details of how the film is formed which would provide information as to the film structure and composition. A PHOSITA would be motivated to look to related art to teach methods for forming a silicon-rich silicon nitride film for Chen’s device and to provide details of the deposited films. Related art from Torchynska teaches forming silicon-rich silicon nitride films using PECVD with ammonia and silane precursors and then annealing the films (which results in crystalline SiN films, although not expressly stated, see Ho et al., entire disclosure, regarding annealing SiN in nitrogen to form crystalline SiN) and that the films comprise both a-Si clusters and crystalline clusters of silicon in the crystalline silicon nitride (see p. 65, col 2 – p. 67 col 1). A PHOSITA would find it obvious to use Torchynska’s PECVD method followed by annealing for forming the semi-insulating silicon-rich silicon nitride film, and this will result in a mixed crystal of silicon nitride and amorphous silicon.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied above, and further in view of Sin et al. (US 2016/0087050)
(Re Claim 6) wherein a thickness of the insulating film is 0.5 micrometers or more and 3.0 micrometers or less.
Chen is silent regarding the thickness of the insulating film. A PHOSITA would be motivated to look to related art to teach a suitable thickness for the insulating film. Related art from Sin teaches the insulating film (31) is about 1 µm thick (¶31). In view of Sin, a PHOSITA would find it obvious to select a thickness of about 1 µm for Chen’s insulating film (5, 51) as this would be obvious to try and have a reasonable expectation of success. The insulating film thickness would be obvious to optimize and ascertainable through routine experimentation, see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). If the film is too thin, it may not provide the necessary insulative and protective properties and may suffer from pinholes, if the film is too thick, this will add unnecessary fabrication time and cost, and thicker films often crack due to stress, thus there will be an optimal film thickness for the device.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied above, and further in view of Saito et al. (US 2016/0329422) and Suzuki et al. (JP 2018-147937).
(Re Claim 12) wherein the semiconductor substrate includes a second surface opposite the first surface in a direction of thickness of the semiconductor substrate;
wherein in the first surface, so as to overlap with the first impurity region in plan view, a first recess recessed toward the second surface is formed; and
wherein the insulating film includes a first insulating film embedded in the first recess and a second insulating film disposed on the first surface so as to cover the first insulating film; and (Re Claim 13) wherein the first insulating film is thicker than the second insulating film.
(Re Claim 14) wherein the semiconductor substrate includes a second surface opposite the first surface in a direction of thickness of the semiconductor substrate;
wherein in the first surface, so as to overlap the first impurity region in plan view,
a plurality of second recesses recessed toward the first surface are formed;
wherein the plurality of second recesses are spaced apart along a direction from the element region toward the termination region; and
wherein the insulating film includes a first insulating film embedded in each of the plurality of second recesses, and a second insulating film disposed on the first surface so as to cover the first insulating film.
Chen is silent regarding spaced apart recesses in the first impurity region (17 and/or 18) filled with an insulating film. A PHOSITA desiring to make, use, and improve upon Chen’s device would be motivated to look to related art for possible modifications. Related art from Saito teaches (Figs. 1-12) forming trenches 54 through the guard ring region 51 in the termination region 50 of the device and filling the trenches with a insulating film 53 and then further covering the structure with an additional insulating film 16. This improves the voltage resistance of the device (¶¶3-17). In view of Saito, a PHOSITA would be motivated to form trenches through Chen’s guard ring regions 17/18, filled with a dielectric, followed by Chen’s insulating film 51 covering the region, in light of Saito, one could form the second insulating film to extend further over the termination region. Related art from Suzuki also similarly teaches forming trenches in the guard ring region and then filling with a first insulating layer followed by a second insulating layer (Fig. 1: 5 and 6) for the same purpose as these features are known to improve the voltage resistance of the device. When incorporating these features into Chen’s guard ring portion/termination region of the device, according to Saito and Suzuki, the first insulating layer will be thicker than the second insulating layer.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied above, and further in view of Luo et al. (US 2018/0269062).
(Re Claim 15) wherein an FRD is formed in the element region.
Chen is silent regarding wherein an FRD is formed in the element region. A PHOSITA would be motivated to look to related IGBT art to teach possible modifications for improvements. Related art from Luo teaches (¶4):
[0004] A reverse conducting IGBT (Insulated Gate Bipolar Transistor) is a new type of IGBT device, in which an IGBT cell structure and an FRD (Fast Recovery Diode) cell structure are integrated on a same chip. The reverse conducting IGBT device has advantages such as a small size, a high power density, a low cost and a high reliability. FIG. 1 shows a top view of a new type of reverse conducting IGBT device, which includes an independent IGBT portion 101 and an independent FRD portion 102 surrounding the IGBT portion 101. In this structure, IGBT cells are provided separately from FRD cells, thereby effectively eliminating negative resistance effect of the reverse conducting IGBT device.
In view of Luo, a PHOSITA would find it obvious to include an FRD in Chen’s element forming region to provide the benefits of a reverse conducting IGBT with advantages such as a small size, a high power density, a low cost and a high reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related devices with structures in termination regions, IGBTs and FRDs, and semi-insulating and silicon-rich silicon nitride layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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